DEI1026 Six Channel Discrete-to-Digital Interface Sensing Open/Ground Signals

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Lynette Warner
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Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ 85225 Phone: (480) 3030822 Fax: (480) 3030824 Email: admin@deiaz.

1 Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ Phone: (480) Fax: (480) DEI1026 Six Channel DiscretetoDigital Interface Sensing Open/Ground Signals Features: Senses six Open/Ground Inputs Inputs are lightning protected to DO160 Level 3 TTL/CMOSCompatible TriState Outputs Package / Temperature Options: 16 lead.150 SOIC, 55 C /85 C 16 lead Ceramic 300mil SOP, 55 C /125 C SOIC package option shown Functional Description: The DEI1026 is a six channel discretetodigital interface BiCMOS device. It senses six Open/Ground discrete signals of the type commonly found in avionic systems. The inverted 3state outputs are TTL/CMOS compatible and are enabled by the OE and CE pins. The inputs are lightning protected to meet the requirements of DO160 Sec 22 Waveforms 3, 4, and 5, Level 3. See figures 57. The device is available in a 16 lead.150 SOIC and.300 Ceramic SOP. With its reliability, low cost, operating range, and lightning protection, the DEI1026 meets a large variety of interface requirements for aerospace applications. OE CE V DD IN 1 1 OUT 1 IN GND IN 2 1 OUT 2 IN OUT 1 IN 3 1 OUT 3 IN OUT 2 IN 4 IN OUT 4 OUT 5 IN 4 IN OUT 3 OUT 4 IN 6 1 OUT 6 IN OUT 5 1 Vdd OE 7 10 OUT 6 3.1V Reference GND CE 8 9 V DD Figure 1: Function Diagram Figure 2: Pinout Diagram 2014 Device Engineering Incorporated Page 1 of 8 DSMW Rev. D

2 Table 1: Absolute Maximum Ratings PARAMETER MIN MAX UNITS Supply Voltage V DD V Discrete Input Voltage (Pins 16) 5 40 * V Digital Input Voltage (CE and OE) V SS 0.3 V DD 0.3 V Lightning Protection (Pins 16) DO160, Waveform 3; Level 3 V DO160, Waveforms 4, and 5; Level 3 Junction Temperature 145 Storage Temperature Plastic Ceramic Operating Free Air Temperature Plastic o C Ceramic The DEI1026 contains circuitry to protect inputs from damage due to electrostatic discharge. It has been characterized per JEDEC A114A Human Body Model to Class 1. Observe precautions for handling and storing Electrostatic Sensitive Devices. * The DEI1026 will withstand the transient surge DC voltage step function loci limits for category B equipment per MIL STD704A. o C o C Table 2: DEI1026 Device Operating Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD V Free Air Operating Temp. T A V DD = V Plastic Ceramic Logic Output Sink Current I OL V DD = V 5.0 ma Logic Output Source Current I OH V DD = V 5.0 ma o C Table 3: DEI1026 Logic Truth Table CE (Chip Enable) OE (Output Enable) Discrete Input Output 0 0 Open Ground 1 1 X X High Z X 1 X High Z 2014 Device Engineering Incorporated Page 2 of 8 DSMW Rev. D

3 Table 4A: DEI1026G (Plastic) Electrical Characteristics (T A = 55 C to 85 C, V DD = 4.5 to 5.5 V, Unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Supply Characteristics Supply Current Ground state input voltage Open state input voltage Ground state input resistor Open state input resistor Input source current I DD V SG V SO R IG R IO I IO V IN = V DD (all inputs) V DD = 5.5 V Discrete Input Characteristics Voltage source from input terminal to ground for Logic High Output. Voltage source from input terminal to ground for Logic Low Output. Resistor from input to ground to guarantee Logic High Output. Resistor from input to ground to guarantee Logic Low Output. Current sourced into 100 Ohm resistor to Ground ma 3.0 V 3.5 V k A Reverse leakage current I IR V IN = 35 V, V DD = 0 V 100 A Logic Input Characteristics CE, OE input logic 1 level V IH 2.0 V CE, OE input logic 0 level V IL 0.8 V DC Output Characteristics Output logic 1 level (TTL) V OH I OH = 5 ma 2.4 V Output logic 0 level (TTL) V OL I OL = 5 ma (2) 0.4 V Output logic 1 level (CMOS) V OH I OH = 100 A V DD 50mV V Output logic 0 level (CMOS) V OL I OL = 100 A V SS 50mV V Offstate Output Current I OZ OE = V DD V DD = 5.5 V V OUT = 0 or V DD Switching Characteristics [1] /10 A I/O propagation delay t HL, t LH Refer to Figure ns output low) to output HIZ output HIZ) to output low output high) to output HI Z output HIZ) to output high t LZ Refer to Figure ns t ZL Refer to Figure ns t HZ Refer to Figure ns t ZH Refer to Figure ns 2014 Device Engineering Incorporated Page 3 of 8 DSMW Rev. D

4 Table 4B: DEI1026WMB (Ceramic) Electrical Characteristics (T A = 55 C to 125 C, V DD = 4.5 to 5.5 V, Unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Supply Characteristics Supply Current Ground state input voltage Open state input voltage Ground state input resistor Open state input resistor Input source current I DD V SG V SO R IG R IO I IO V IN = V DD (all inputs) V DD = 5.5 V Discrete Input Characteristics Voltage source from input terminal to ground for Logic High Output. Voltage source from input terminal to ground for Logic Low Output. Resistor from input to ground to guarantee Logic High Output. Resistor from input to ground to guarantee Logic Low Output. Current sourced into 100 Ohm resistor to Ground ma 3.0 V 3.5 V k A Reverse leakage current I IR V IN = 35 V, V DD = 0 V 100 A Logic Input Characteristics CE, OE input logic 1 level V IH 2.0 V CE, OE input logic 0 level V IL 0.8 V DC Output Characteristics Output logic 1 level (TTL) V OH I OH = 5 ma 2.4 V Output logic 0 level (TTL) V OL I OL = 5 ma (2) 0.4 V Output logic 1 level (CMOS) V OH I OH = 100 A V DD 50mV V Output logic 0 level (CMOS) V OL I OL = 100 A V SS 50mV V Offstate Output Current I OE = V DD OZ V DD = 5.5 V V OUT = 0 or V DD Switching Characteristics [1] /10 A I/O propagation delay t HL, t LH Refer to Figure ns output low) to output HIZ output HIZ) to output low output high) to output HI Z output HIZ) to output high Notes: t LZ Refer to Figure ns t ZL Refer to Figure ns t HZ Refer to Figure ns t ZH Refer to Figure ns 1. Guaranteed by design and not production tested. 2. Limit the sum of all IOL currents to 20ma. The Vsg spec may exceed limit beyond this current Device Engineering Incorporated Page 4 of 8 DSMW Rev. D

5 2014 Device Engineering Incorporated Page 5 of 8 DSMW Rev. D

6 DO160 DO160 DO160 PACKAGE TYPE 16 Lead SOIC Narrow Body, Green 16 Lead Ceramic SOP REFERENCE 16L SOIC NB G 16L CSOP THERMAL RESISTANCE: JA (4 layer PCB with Power Planes) 74 C/W JC 24 C/W 23 C/W JEDEC MOISTURE SENSITIVITY LEVEL (MSL) LEAD FINISH MATERIAL / JEDEC Pbfree CODE MSL 1 / 260 C NiPdAu e4 Hermetic Au e4 PbFree DESIGNATION RoHS Compliant Pb Free JEDEC REFERENCE MS012AC 2014 Device Engineering Incorporated Page 6 of 8 DSMW Rev. D

7 Figure 8: Mechanical Outline, 16 lead SOIC G Package Figure 9: Mechanical Outline, 16 lead Ceramic SOP 2014 Device Engineering Incorporated Page 7 of 8 DSMW Rev. D

8 DEI PART NUMBER DEI1026G MARKING (1) DEI1026 E4 (2) Table 6: Ordering Information PACKAGE DEI1026WMB DEI1026WMB 16 lead ceramic SOP NOTES: 1. All packages marked with Lot Code and Date Code. 2. E4 after Date Code Denotes Pb Free category. OP. TEMP. RANGE PROCESSING 16L SOIC NB G 55 / 85ºC Standard 55 / 125ºC Burn In, 96 DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose Device Engineering Incorporated Page 8 of 8 DSMW Rev. D

DEI1026A Six Channel Discrete-to-Digital Interface Sensing Open/Ground Signals

DEI1026A Six Channel Discrete-to-Digital Interface Sensing Open/Ground Signals Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ 85225 Phone: (480) 3030822 Fax: (480) 3030824 Email: admin@deiaz.com DEI1026A Six Channel DiscretetoDigital Interface Sensing Open/Ground