ISL6700. Preliminary. 80V, 1.25A Peak Current Half-Bridge MOSFET Driver. itle P40. Features. Description. b- t V, 5A k r- thdge. T ver) Applications

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1 TM itle P40 b- t V, 5A k r- thdge T ver) thor y- rds ter- i- - tor, 40, l dge, Preliminary January 16, 2002 Features Drives 2 N-Channel MOSFETs in Half-Bridge Configuration Bootstrap Supply Max Voltage to 96VDC and Phase Max Voltage to 80VDC Drives 1000pF Load in Free Air at 50 o C with Rise and Fall Times of Typically 15ns Independent control of and HO outputs Input Logic Thresholds Compatible with 5V to 15V Logic Levels Undervoltage Protection Applications Half-Bridge DC-DC Converters 2-Switch Forward DC-DC Converters Synchronous Buck DC-DC Converters Description 80V, 1.25A Peak Current Half-Bridge MOSFET Driver The is a medium frequency, medium voltage Half-Bridge N-Channel MOSFET driver IC, available in 8 lead plastic SOIC (N) package. With operation up to 80V, the device is best suited to applications of moderate power levels. The does not contain an internal charge pump, but does incorporate non-latching level-shift translation control of the upper drive circuit. This set of features and specifications is optimized for applications where size and cost are important.. Ordering Information PART NUMBER IB IR TEMPERATURE RANGE -40 o C to +125 o C -40 o C to +125 o C PACKAGE 8 Lead Plastic SOIC 12 Lead 4x4 MLFP dge, dge, fig- -, ver, - v-, e, Pinout VDD HI VSS IB SOIC TOP VIEW HB HO HS Application Block Diagram 12V VDD HB HI HO HS 75V To Load VSS GND GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Corporation File Number

2 Functional Block Diagram HB U/V LEVEL SHIFT DRIVER HO HS HI V SS Turn-On Delay DRIVER V DD V SS DETECTOR UNDERVOLTAGE V SS Typical Application 2

3 Specifications (Preliminary) Absolute Maximum Ratings Supply Voltage, V DD Vto16V Logic I/O Voltages VtoV DD +0.3V VoltageonHS Vto80V(-40 o C to150 o C) VoltageonHB...V HS, -0.3V to V HS, +V DD Voltageon...V SS -0.3V to V DD +0.3V VoltageonHO...V HS -0.3V to V HB +0.3V Input PhaseSlewRate...20V/ns NOTE: All voltages are relative V SS unless otherwise specified. Thermal Information Thermal Resistance, Junction-Ambient θ JA SOICPackage o C/W (1S0P board) 95 o C/W (1S2P board) MLFPPackage o C/W (1S2P board) MaximumPowerDissipation...TBD Storage Temperature Range o C to +150 o C OperatingMax.JunctionTemperature o C Lead Temperature (Soldering 10s) o C (For SOIC - Lead Tips Only)) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Supply Voltage, V DD... +9Vto+15V Voltage on V SS Vto+1.0V VoltageonHS V VoltageonHB...V HS +7.5V to V HS +V DD Preliminary Electrical Specifications V DD =V HB = 12V, V SS =V HS =0V T J =+25 o C T J =-40 o C To +125 o C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS & UNDER VOLTAGE PROTECTION V DD Quiescent Current I DD =0 or VDD ma V DD Operating Current I DDO f=50khz,noload ma V DD Operating Current I DDO f = 500kHz, No Load 4 5 ma HB Off Quiescent Current I HBL HI = ma HB On Quiescent Current I HBH HI = VDD µa HB Operating Current I HBO f=50khz,c L = 1000pF ma HB Operating Current I HBO f = 500kHz, C L = 1000pF ma HS Leakage Current I HLK V HS = 80V µa V HB = = 96V V DD Rising Undervoltage Threshold V DDUV V V DD Falling Undervoltage Threshold V DDUV V Undervoltage Hysteresis UVHYS V HB Undervoltage Threshold VHBUV Referenced to HS V INPUT PINS: and HI Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current (Revised Part) I IL V IN =0V, Full Operating Conditions µa High Level Input Current (Revised Part) I IH VIN=5V, Full Operating Conditions µa GATE DRIVER OUTPUT PINS: & HO Low Level Output Voltage V OL I OUT = V High Level Output Voltage V DD -V OH I OUT = V Peak Pullup Current I O + V OUT =0V 1.4 A Peak Pulldown Current I O - V OUT = 12V 1.3 A 3

4 Specifications (Preliminary) Switching Specifications V DD =V HB = 12V, V SS =V HS = 0V, No Load. T J =+25 o C T J =-40 o C To +125 o C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (-,) Upper Turn-off Propagation Delay (HI-HO,) Lower Turn-on Propagation Delay (-) Upper Turn-on Propagation Delay (HI-HO) T LPHL ns T HPHL ns T LPLH ns T HPLH ns Deadtime, (T HPLH -T LPHL ) DHTon, HI switched simultaneously 0 0 Deadtime, (T LPLH -T HPHL ) DLTon 0 0 Rise Time T R No Load ns Fall Time T F No Load ns Minimum Input Pulse Width T PWIN-ON/OFF ns Output Pulse Response to 80 ns Input Pulse T PWOUT ns Delay Matching: Lower Turn-on and Upper Turnon Delay Matching: Lower Turn-off and Upper Turnoff MT ns MT ns TRUTH TABLE INPUT 1 OUTPUT HI VDDUV VHBUV HO X X 1 X X X 1 0 NOTE: Note 1: X signifies that input can be either a 1 or 0. For UV functions a 1 signifies an undervoltage lockout condition, a 0 signifies the supply is at proper operating range. 4

5 Pin Descriptions SOIC PIN NUMBER SYMBOL DESCRIPTION 8 HB High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. 3 Logic level input that controls the output. The pin can be driven by signal levels of -.3V to VDD +.3V. 2 HI Logic level input that controls the HO output. The HI pin can be driven by signal levels of -.3V to VDD +.3V. 4 V SS Chip negative supply, generally will be ground. 1 V DD Positive supply to control logic and lower gate drivers. De-couple this pin to V SS. 5 Low-side Output. Connect to gate Low-side power MOSFET. 6 HS High-side Source connection. Connect to source of High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 7 HO High-side Output. Connect to gate of High-side power MOSFET. 5

6 Timing Diagram T LPHL T HPHL UV=0 HI HO T HPLH T LPLH T R (10% - 90%) T F (10% - 90%) FIGURE 1. Timing Diagram Revisons: 3/29/01: Added proposed pinout 5/23/01: Corrected test conditions, added pulsewidth and matching specs, corrected truth table, added thermal impedances 7/18: Fixed Vil spec (columns were switched) 8/5/01: Corrected title to 75V to match recommended operating range 9/13/01: Changed IIH spec to reflect added input pulldowns, adjusted supply currents and added 500KHz supply current specs. Changed Absolute Max on HS from -6V (transient) to -1V (due to added ESD clamps and their breakdown voltages) : Changed HS and VDD voltages to reflect revised design : Revised for Rev B FOK electricals. 6