HIP V/2.5A Peak, High Frequency Full Bridge FET Driver. Features. Description. Applications. Ordering Information

Transcription

1 November V/.5A Peak, High Frequency Full Bridge FET Driver Features Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations Bootstrap Supply Max Voltage to 95V DC Drives 000pF Load at MHz in Free Air at 50 o C with Rise and Fall Times of Typically 0ns User-Programmable Dead Time On-Chip Charge-Pump and Bootstrap Upper Bias Supplies (Disable) Overrides Input Control Input Logic Thresholds Compatible with 5V to 5V Logic Levels Very Low Power Consumption Applications Medium/Large Voice Coil Motors Full Bridge Power Supplies Class D Audio Power Amplifiers High Performance Motor Controls Noise Cancellation Systems Battery Powered Vehicles Peripherals U.P.S. Ordering Information Description The HIP408 is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 0 lead plastic SOIC and DIP packages. The HIP408 can drive every possible switch combination except those which would cause a shoot-through condition. The HIP408 can switch at frequencies up to MHz andssssss is well suited to driving Voice Coil Motors, high-frequency Class D audio amplifiers, and power supplies. For example, the HIP408 can drive medium voltage brush motors, and two HIP408s can be used to drive high performance stepper motors, since the short minimum on-time can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load. A similar part, the HIP4080, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate hysteresis mode switching. See Application Note AN95 for HIP408, Intersil Answer- FAX, (407) , document #995. Intersil web home page: Similar part HIP408A includes undervoltage circuitry which does not require the circuitry shown in Figure 0 of this data sheet. PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NUMBER HIP408IP -40 to 85 0 Lead Plastic DIP E0. HIP408IB -40 to 85 0 Lead Plastic SOIC M0. Pinout HIP408 (PDIP, SOIC) TOP VIEW BHB 0 BHO BHI 9 BHS 8 BLO V SS 4 7 BLS BLI 5 6 V DD ALI 6 5 V CC AHI 7 4 ALS HDEL 8 ALO LDEL 9 AHS AHB 0 AHO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. or Copyright Intersil Corporation 999 File Number 556.7

2 Application Block Diagram 80V V BHO BHS BHI BLO BLI HIP408 LOAD ALI AHI ALO AHS AHO GND GND Functional Block Diagram (/ HIP408) HIGH VOLTAGE BUS 80V DC 0 AHB CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER AHO C BS V DD 6 AHS AHI 7 TURN-ON DELAY 5 V CC D BS TO V DD (PIN 6) ALI 6 TURN-ON DELAY DRIVER 4 ALO ALS C BF +V DC BIAS SUPPLY HDEL 8 LDEL 9 V SS 4

3 Typical Application (PWM Mode Switching) HIP408 80V V BHB BHI BHO BHS BLO LOAD PWM INPUT V SS BLI ALI AHI HDEL LDEL AHB BLS V DD V CC ALS ALO AHS AHO V GND TO OPTIONAL CURRENT CONTROLLER - + 6V GND

4 Absolute Maximum Ratings Thermal Information (Typical, Note ) Supply Voltage, V DD and V CC V to 6V Logic I/O Voltages V to V DD +0.V Voltage on AHS, BHS V (Transient) to 80V (5 o C to 5 o C) Voltage on AHS, BHS V (Transient) to 70V (-55 o C to 5 o C) Voltage on ALS, BLS V (Transient) to +.0V (Transient) Voltage on AHB, BHB V AHS, BHS -0.V to V AHS, BHS +6V Voltage on ALO, BLO V ALS, BLS -0.V to V CC +0.V Voltage on AHO, BHO......V AHS, BHS -0.V to V AHB, BHB +0.V Input Current, HDEL and LDEL mA to 0mA Phase Slew Rate V/ns NOTE: All voltages are relative to pin 4, V SS, unless otherwise specified. Storage Temperature Range o C to 50 o C Operating Max. Junction Temperature o C Lead Temperature (Soldering 0s) o C (For SOIC - Lead Tips Only) Thermal Resistance, Junction-Ambient SOIC Package o C/W DIP Package o C/W CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. Operating Conditions Supply Voltage, V DD and V CC V to +5V Voltage on ALS, BLS V to +.0V Voltage on AHB, BHB V AHS, BHS +5V to V AHS, BHS +5V Input Current, HDEL and LDEL µA to -50µA Operating Ambient Temperature Range o C to 85 o C Electrical Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 o C, Unless Otherwise Specified T J = 5 o C T JS = -40 o C TO 5 o C PARAMETER SYMBOL TEST CONDITIONS SUPPLY CURRENTS AND CHARGE PUMPS MIN TYP MAX MIN MAX UNITS V DD Quiescent Current I DD All Inputs = 0V ma V DD Operating Current I DDO Outputs Switching f = 500kHz ma V CC Quiescent Current I CC All Inputs = 0V, I ALO = I BLO = µa V CC Operating Current I CCO f = 500kHz, No Load ma AHB, BHB Quiescent Current - Qpump Output Current I AHB, I BHB All Inputs = 0V, I AHO = I BHO = 0 V DD = V CC = V AHB = V BHB = 0V µa AHB, BHB Operating Current I AHBO, I BHBO f = 500kHz, No Load ma AHS, BHS, AHB, BHB Leakage Current I HLK V AHS = V BHS = V AHB = V BHB = 95V µa AHB-AHS, BHB-BHS Qpump Output Voltage V AHB -V AHS I AHB = I AHB = 0, No Load V V BHB -V BHS INPUT PINS: ALI, BLI, AHI, BHI, AND Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current I IL V IN = 0V, Full Operating Conditions µa High Level Input Current I IH V IN = 5V, Full Operating Conditions µa TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V HDEL, V LDEL I HDEL = I LDEL = -00µA V GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage V OL I OUT = 00mA V High Level Output Voltage V CC -V OH I OUT = -00mA V 4

5 Electrical Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 o C, Unless Otherwise Specified (Continued) T J = 5 o C T JS = -40 o C TO 5 o C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Peak Pullup Current I O + V OUT = 0V A Peak Pulldown Current I O - V OUT = V A Switching Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K, C L = 000pF T J = +5 o C T JS = 40 o C TO 5 o C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) T LPHL ns T HPHL ns T LPLH ns T HPLH ns Rise Time T R ns Fall Time T F ns Turn-on Input Pulse Width T PWIN-ON ns Turn-off Input Pulse Width T PWIN-OFF ns Disable Turn-off Propagation Delay ( - Lower Outputs) Disable Turn-off Propagation Delay ( - Upper Outputs) Disable to Lower Turn-on Propagation Delay ( - ALO and BLO) T LOW ns T HIGH ns T DLPLH ns Refresh Pulse Width (ALO and BLO) T REF-PW ns Disable to Upper Enable ( - AHO and BHO) T HEN ns TRUTH TABLE INPUT OUTPUT ALI, BLI AHI, BHI ALO, BLO AHO, BHO X X 0 0 X NOTE: X signifies that input can be either a or 0. 5

6 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. BHI B High-side Input. Logic level input that controls BHO driver (Pin 0). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. (Pin ) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). An internal 00µA pull-up to V DD will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input. Disable input. Logic level input that when taken high sets all four outputs low. high overrides all other inputs. When is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). An internal 00µA pull-up to V DD will hold high if this pin is not driven. 4 V SS Chip negative supply, generally will be ground. 5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 8). If BHI (Pin ) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). (Pin ) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). An internal 00µA pull-up to V DD will hold BLI high if this pin is not driven. 6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin ). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). (Pin ) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). An internal 00µA pull-up to V DD will hold ALI high if this pin is not driven. 7 AHI A High-side Input. Logic level input that controls AHO driver (Pin ). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. (Pin ) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). An internal 00µA pull-up to V DD will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.V. 0 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. AHO A High-side Output. Connect to gate of A High-side power MOSFET. AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 4 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 5 V CC Positive supply to gate drivers. Must be same potential as V DD (Pin 6). Connect to anodes of two bootstrap diodes. 6 V DD Positive supply to lower gate drivers. Must be same potential as V CC (Pin 5). De-couple this pin to V SS (Pin 4). 7 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 8 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 9 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 0 BHO B High-side Output. Connect to gate of B High-side power MOSFET. 6

7 Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT T LPHL T HPHL = 0 XLI XHI XLO XHO T HPLH T LPLH T R (0% - 90%) T F (0% - 90%) FIGURE. INDEPENDENT MODE = 0 XLI XHI = HI OR NOT CONNECTED XLO XHO FIGURE. BISTATE MODE T DLPLH T T REF-PW XLI XHI XLO XHO T HEN FIGURE. ABLE FUNCTION 7

8 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 o C, Unless Otherwise Specified I DD SUPPLY CURRENT (ma) SUPPLY CURRENT (ma) V DD SUPPLY VOLTAGE (V) SWITCHING FREQUENCY (khz) FLOATING SUPPLY BIAS CURRENT (ma) FIGURE 4. QUIESCENT I DD SUPPLY CURRENT vs V DD SUPPLY VOLTAGE SWITCHING FREQUENCY (khz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 000pF) I CC SUPPLY CURRENT (ma) FIGURE 5. I DDO, NO-LOAD I DD SUPPLY CURRENT vs FREQUENCY (khz) o C 75 o C 5 o C 0 o C -40 o C SWITCHING FREQUENCY (khz) FIGURE 7. I CCO, NO-LOAD I CC SUPPLY CURRENT vs FREQUENCY (khz) TEMPERATURE FLOATING SUPPLY BIAS CURRENT (ma) SWITCHING FREQUENCY (khz) LOW LEVEL INPUT CURRENT (µa) FIGURE 8. I AHB, I BHB NO-LOAD FLOATING SUPPLY CURRENT vs FREQUENCE FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT I IL vs TEMPERATURE 8

9 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 o C, Unless Otherwise Specified (Continued) NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) PROPAGATION DELAY (ns) FIGURE 0. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE FIGURE. UPPER ABLE TURN-OFF PROPAGATION DELAY T HIGH vs TEMPERATURE PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE. ABLE TO UPPER ENABLE T UEN PROPAGATION DELAY vs TEMPERATURE FIGURE. ABLE TO UPPER ENABLE T UEN PROPAGATION DELAY vs TEMPERATURE REFRESH PULSE WIDTH (ns) PROPAGATION DELAY (ns) FIGURE 4. T REF-PW REFRESH PULSE WIDTH vs TEMPERATURE FIGURE 5. ABLE TO LOWER ENABLE T DLPLH PROPAGATION DELAY vs TEMPERATURE 9

10 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 o C, Unless Otherwise Specified (Continued) PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE 6. UPPER TURN-OFF PROPAGATION DELAY T HPHL vs TEMPERATURE FIGURE 7. UPPER TURN-ON PROPAGATION DELAY T HPLH vs TEMPERATURE PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE 8. LOWER TURN-OFF PROPAGATION DELAY T LPHL vs TEMPERATURE FIGURE 9. LOWER TURN-ON PROPAGATION DELAY T LPLH vs TEMPERATURE.5.5 GATE DRIVE FALL TIME (ns) TURN-ON RISE TIME (ns) FIGURE 0. GATE DRIVE FALL TIME T F vs TEMPERATURE FIGURE. GATE DRIVE RISE TIME T R vs TEMPERATURE 0

11 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 o C, Unless Otherwise Specified (Continued) HDEL, LDEL INPUT VOLTAGE (V) V CC - V OH (mv) o C 0 o C 5 o C 75 o C 5 o C BIAS SUPPLY VOLTAGE (V) FIGURE. V LDEL, V HDEL VOLTAGE vs TEMPERATURE FIGURE. HIGH LEVEL OUTPUT VOLTAGE V CC - V OH vs BIAS SUPPLY AND TEMPERATURE AT 00mA V OL (mv) o C 0 o C 5 o C 75 o C GATE DRIVE SINK CURRENT (A) o C BIAS SUPPLY VOLTAGE (V) V DD, V CC, V AHB, V BHB (V) FIGURE 4. LOW LEVEL OUTPUT VOLTAGE V OL vs BIAS SUPPLY AND TEMPERTURE AT 00mA FIGURE 5. PEAK PULLDOWN CURRENT I O vs BIAS SUPPLY VOLTAGE GATE DRIVE SINK CURRENT (A) V DD, V CC, V AHB, V BHB (V) LOW VOLTAGE BIAS CURRENT (ma) ,000pF,000pF,000pF 00pF SWITCHING FREQUENCY (khz) FIGURE 6. PEAK PULLUP CURRENT I O+ vs BIAS SUPPLY VOLTAGE FIGURE 7. LOW VOLTAGE BIAS CURRENT I DD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE

12 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 o C, Unless Otherwise Specified (Continued) LEVEL-SHIFT CURRENT (µa) V 60V 40V 0V SWITCHING FREQUENCY (khz) DEAD-TIME (ns) HDEL/LDEL RESISTANCE (kω) FIGURE 8. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE FIGURE 9. MINIMUM DEAD-TIME vs DEL RESISTANCE HI408 Power-up Application Information The HIP408 H-Bridge Driver IC requires external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOS- FETs may be exposed to shoot-through current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. The HIP408 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure 0. As the V DD /V CC supply ramps from zero up, the voltage is below its input threshold of.7v due to the R/R resistor divider. When V DD /V CC exceeds approximately 9V to 0V, becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low prior to reaching its threshold level of.7v while V DD /V CC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the pin low. ENABLE V DD ALI, BLI R 5K R.K BHB BHI 4 V SS 5 BLI 6 ALI AHI HDEL LDEL 0 AHB FIGURE 0A. BHO 0 BHS 9 BLO 8 BLS 7 V DD 6 V CC 5 ALS 4 ALO AHS AHO 8.5V TO 0.5V (ASSUMES 5% RESISTORS).7V V, FINAL VALUE t NOTES:. ALI and/or BLI may be high after t, whereupon the ENABLE pin may also be brought high.. Another product, HIP408A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry. FIGURE 0B. TIMING DIAGRAM FOR FIGURE 0A

13 IN IN +V POWER SECTION B+ 5 ENABLE IN I R CONTROL LOGIC SECTION U CD4069UB U CD4069UB U CD4069UB U CD4069UB 9 U CD4069UB U 8 R9 JMPR OUT/BLI JMPR IN+/ALI JMPR HEN/BHI JMPR4 IN-/AHI O O 5K.K JMPR5 R CW TO PIN + C6 R4 CW DRIVER SECTION HIP4080/8 U C BHB HEN/BHI V SS OUT/BLI IN+/ALI IN-/AHI HDEL LDEL AHB BHO 0 BHS 9 BLO 8 BLS 7 V 6 DD V 5 CC ALS 4 ALO AHS AHO CR C C5 +V CR ALS R R R R4 CX BLS Q Q CY R0 Q L C Q4 C8 L C R AO BO COM HIP408 CD4069UB NOTES: 4. Device CD4069UB PIN 7 = COM, Pin 4 = +V. 5. Components L, L, C, C, CX, CY, R0, R, not supplied. refer to Application Note for description of input logic operation to determine jumper locations for JMPR - JMPR4. FIGURE. HIP408 EVALUATION BOARD SCHEMATIC

14 GND +V B+ COM 4 IR IN O IN R9 C7 JMPR5 R7 R8 R6 C6 + + U U JMPR JMPR JMPR JMPR4 O LDEL CR HIP4080/8 C4 BHO BLO BLS ALS ALO C AHO C8 Q Q R R4 R Q Q4 R L L C C AO BO HIP408 ALS HDEL CR C5 CX CY BLS R R4 R0 R FIGURE. HIP408 EVALUATION BOARD SILKSCREEN

15 Supplemental Information for HIP4080 and HIP408 Power Application The HIP4080 and HIP408 H-Bridge Driver ICs require external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOSFETs may be exposed to shootthrough current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. HIP408 The HIP408 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure. As the V DD /V CC supply ramps from zero up, the voltage is below its input threshold of.7v due to the R/R resistor divider. When V DD /V CC exceeds approximately 9V to 0V, becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low prior to reaching its threshold level of.7v while V DD /V CC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the pin low. HIP4080 The HIP4080 does not have an input protocol like the HIP408 that keeps both lower power MOSFETs off other than through the pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming is low. However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL, while the chip is enabled, as shown in Figure 4. Pulling LDEL to V DD will indefinitely delay the lower turn-on delays through the input comparator and will keep the lower MOS- FETs off. With the lower MOSFETs off and the chip enabled, i.e., = low, IN+ or IN- can be switched through a full cycle, properly setting the upper driver outputs. Once this is accomplished, LDEL is released to its normal operating point. It is critical that IN+/IN- switch a full cycle while LDEL is held high, to avoid shoot-through. This start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in Figure. ENABLE R 5K R.K BHB BHI 4 V SS 5 BLI 6 ALI BHO 0 BHS 9 BLO 8 BLS 7 V DD 6 V CC 5 ENABLE R 5K R.K BHB BHI 4 V SS 5 BLI 6 ALI BHO 0 BHS 9 BLO 8 BLS 7 V DD 6 V CC AHI HDEL ALS 4 ALO 7 8 AHI HDEL ALS 4 ALO 9 LDEL 0 AHB AHS AHO 9 LDEL 0 AHB AHS AHO FIGURE. V DD V DD ENABLE BHB HEN BHO 0 BHS 9 BLO 8 56K 8.V 56K N906 00K 00K 0.µF V DD RDEL RDEL 4 V SS 5 OUT 6 IN+ 7 IN- 8 HDEL 9 LDEL 0 AHB BLS 7 V DD 6 V CC 5 ALS 4 ALO AHS AHO FIGURE 4. 5

16 Timing Diagrams V DD V, FINAL VALUE V DD V, FINAL VALUE 8.5V TO 0.5V (ASSUMES 5% RESISTORS) 8.V TO 9.V (ASSUMING 5% ZENER TOLERANCE) ALI, BLI LDEL.7V =0ms t t 5.V NOTE: 6. ALI and/or BLI may be high after t, whereupon the ENABLE pin may also be brought high. FIGURE 5. NOTE: 7. Between t and t the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If the ENABLE pin is low after the undervoltage circuit is satisfied, the ENABLE pin will initiate the 0ms time delay during which the IN+ and IN- pins must cycle at least once. FIGURE 6. 6

17 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B N N/ B D e D -C- -A- NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.5mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E4.6 will have a B dimension of inch ( mm). E -B- A 0.00 (0.5) M C A A L B S A e C E C L e A e B C E0. (JEDEC MS-00-AD ISSUE D) 0 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e 0.00 BSC.54 BSC - e A 0.00 BSC 7.6 BSC 6 e B L N Rev. 0 /9 7

18 Small Outline Plastic Packages (SOIC) HIP408 N INDEX AREA e D B 0.5(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.5(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.5mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.6mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.04 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α L M h x 45 o C M0. (JEDEC MS-0-AC ISSUE C) 0 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e BSC.7 BSC - H h L N α 0 o 8 o 0 o 8 o - Rev. 0 /9 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 88, Mail Stop 5-04 Melbourne, FL 90 TEL: (407) FAX: (407) For information regarding Intersil Corporation and its products, see web site EUROPE Intersil SA Mercure Center 00, Rue de la Fusee 0 Brussels, Belgium TEL: ().74. FAX: () ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 0 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) FAX: (886)