Features PART MARKING. PKG. DWG. # HIP2100IB (No longer available, recommended replacements: HIP2100IBZ, HIP2100IBZT)

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1 DATASHEET 00V/2A Peak, Low ost, High Frequency Half Bridge Driver FN4022 Rev 5.00 The is a high frequency, 00V Half Bridge N-hannel power MOSFET driver I. The low-side and high-side gate drivers are independently controlled and matched to 8ns. This gives the user maximum flexibility in dead-time selection and driver protocol. Undervoltage protection on both the low-side and high-side supplies force the outputs low. An on-chip diode eliminates the discrete diode required with other driver Is. A new level-shifter topology yields the low-power benefits of pulsed operation with the safety of D operation. Unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply. Applications Telecom Half Bridge Power Supplies Avionics D/D onverters Two-Switch Forward onverters Active lamp Forward onverters Features Drives N-hannel MOSFET Half Bridge SOI, EPSOI, QFN and DFN Package Options SOI, EPSOI and DFN Packages ompliant with 00V onductor Spacing Guidelines of IP-222 Pb-Free Product Available (RoHS ompliant) Bootstrap Supply Max Voltage to 4VD On-hip Bootstrap Diode Fast Propagation Times for Multi-MHz ircuits Drives 000pF Load with Rise and Fall Times Typ. 0ns MOS Input Thresholds for Improved Noise Immunity Independent Inputs for Non-Half Bridge Topologies No Start-Up Problems Outputs Unaffected by Supply Glitches, HS Ringing Below Ground, or HS Slewing at High dv/dt Low Power onsumption Wide Supply Range Supply Undervoltage Protection 3 Driver Output Resistance QFN/DFN Package: - ompliant to JEDE PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near hip Scale Package Footprint, which Improves PB Efficiency and has a Thinner Profile - Ordering Information PART NUMBER (Note ) PART MARKING TEMP. RANGE ( ) PAKAGE PKG. DWG. # IB (No longer available, recommended replacements: IBZ, IBZT) 200 IB -40 to Ld SOI M8.5 IBZ (Note 2) 200 IBZ -40 to Ld SOI (Pb-free) M8.5 EIBZ (Note 2) 200 EIBZ -40 to Ld EPSOI (Pb-free) M8.5 IRZ (Note 2) P 200IRZ -40 to Ld 5x5 QFN (Pb-free) L6.5x5 IR4Z (Note 2) (No longer available, recommended replacements: IRZ, IRZT) 2 00IR4Z -40 to Ld 4x4 DFN (Pb-free) L2.4x4A NOTES:. Add T suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 00% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-020. FN4022 Rev 5.00 Page of 3

2 Pinouts (8 LD SOI, EPSOI) TOP VIEW IR4 (2 LD DFN) TOP VIEW (6 LD QFN) TOP VIEW V DD HB HS EPAD NOTE: EPAD = Exposed PAD V SS V DD HB HS EPAD 2 V SS NO NGER AVAILABLE OR SUPPORTED) 6 7 HB V DD EPAD V SS HS Application Block Diagram +2V +00V V DD HB SEONDARY IRUIT PWM ONTROLLER ONTROL DRIVE DRIVE HS V SS REFEREE AND ISOLATION FN4022 Rev 5.00 Page 2 of 3

3 Functional Block Diagram HB V DD UNDER VOLTAGE LEVEL SFT DRIVER HS UNDER VOLTAGE DRIVER V SS EPAD (EPSOI, QFN and DFN PAKAGES ONLY) *EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PB power ground plane. +48V +2V PWM SEONDARY IRUIT ISOLATION FIGURE. TWO-SWITH FORWARD ONVERTER +48V +2V SEONDARY IRUIT PWM ISOLATION FIGURE 2. FORWARD ONVERTER WITH AN ATIVE LAMP FN4022 Rev 5.00 Page 3 of 3

4 Absolute Maximum Ratings Supply Voltage, V DD, V HB -V HS (Notes 3, 4) V to 8V and Voltages (Note 4) V to V DD +0.3V Voltage on (Note 4) V to V DD +0.3V Voltage on (Note 4) V HS -0.3V to V HB +0.3V Voltage on HS (ontinuous) (Note 4) V to 0V Voltage on HB (Note 4) V Average urrent in V DD to HB diode mA ESD lassification lass (kv) Maximum Recommended Operating onditions Supply Voltage, V DD V to 4.0VD Voltage on HS V to 00V Voltage on HS (Repetitive Transient) -5V to 05V Voltage on HB... V HS +8V to V HS +4.0V and V DD -V to V DD +00V HS Slew Rate <50V/ns Thermal Information Thermal Resistance (Typical) JA ( /W) J ( /W) SOI (Note 5) EPSOI (Note 6) QFN (Note 6) DFN (Note 6) Max Power Dissipation at +25 in Free Air (SOI, Note 5).....3W Max Power Dissipation at +25 in Free Air (EPSOI, Note 6).. 3.W Max Power Dissipation at +25 in Free Air (QFN, Note 6) W Storage Temperature Range to +50 Junction Temperature Range to +50 Pb-Free Reflow Profile see link below AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. The is capable of derated operation at supply voltages exceeding 4V. Figure 6 shows the high-side voltage derating curve for this mode of operation. 4. All voltages referenced to V SS unless otherwise specified. 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. J, the case temp is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications V DD = V HB = 2V, V SS = V HS = 0V, No Load on or, Unless Otherwise Specified. T J = +25 T J = -40 TO +25 PARAMETERS SYMBOL TEST ONDITIONS MIN TYP MAX MIN (Note 7) MAX (Note 7) UNITS SUPPLY URRENTS V DD Quiescent urrent I DD = = 0V ma V DD Operating urrent I DDO f = 500kHz ma Total HB Quiescent urrent I HB = = 0V ma Total HB Operating urrent I HBO f = 500kHz ma HB to V SS urrent, Quiescent I HBS V HS = V HB = 4V µa HB to V SS urrent, Operating I HBSO f = 500kHz ma INPUT PINS Low Level Input Voltage Threshold V IL V High Level Input Voltage Threshold V IH V Input Voltage Hysteresis V IHYS V Input Pulldown Resistance R I k UNDERVOLTAGE PROTETION V DD Rising Threshold V DDR V V DD Threshold Hysteresis V DDH V HB Rising Threshold V HBR V HB Threshold Hysteresis V HBH V FN4022 Rev 5.00 Page 4 of 3

5 Electrical Specifications V DD = V HB = 2V, V SS = V HS = 0V, No Load on or, Unless Otherwise Specified. (ontinued) T J = +25 T J = -40 TO +25 PARAMETERS SYMBOL TEST ONDITIONS MIN TYP MAX MIN (Note 7) MAX (Note 7) UNITS BOOT STRAP DIODE Low-urrent Forward Voltage V DL I VDD-HB = 00µA V High-urrent Forward Voltage V DH I VDD-HB = 00mA V Dynamic Resistance R D I VDD-HB = 00mA GATE DRIVER Low Level Output Voltage V OLL I = 00mA V High Level Output Voltage V OHL I = -00mA, V OHL = V DD -V V Peak Pullup urrent I OHL V = 0V A Peak Pulldown urrent I OLL V = 2V A GATE DRIVER Low Level Output Voltage V OLH I = 00mA V High Level Output Voltage V OHH I = -00mA, V OHH = V HB -V V Peak Pullup urrent I OHH V = 0V A Peak Pulldown urrent I OLH V = 2V A Switching Specifications V DD = V HB = 2V, V SS = V HS = 0V, No Load on or, Unless Otherwise Specified. T J = +25 T J = -40 TO +25 PARAMETERS SYMBOL TEST ONDITIONS MIN TYP MAX MIN (Note 7) MAX (Note 7) UNITS Lower Turn-Off Propagation Delay ( Falling to Falling) t LPHL ns Upper Turn-Off Propagation Delay ( Falling to Falling) t HPHL ns Lower Turn-On Propagation Delay ( Rising to Rising) t LPLH ns Upper Turn-On Propagation Delay ( Rising to Rising) t HPLH ns Delay Matching: Lower Turn-On and Upper Turn-Off t MON ns Delay Matching: Lower Turn-Off and Upper Turn-On t MOFF ns Either Output Rise/Fall Time t R, t F L = 000pF ns Either Output Rise/Fall Time (3V to 9V) t R, t F L = 0.µF µs Either Output Rise Time Driving DMOS t RD L = IRFR ns Either Output Fall Time Driving DMOS t FD L = IRFR ns Minimum Input Pulse Width that hanges the Output t PW ns Bootstrap Diode Turn-On or Turn-Off Time t BS ns NOTE: 7. Parameters with MIN and/or MAX limits are 00% tested at +25, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN4022 Rev 5.00 Page 5 of 3

6 Pin Descriptions SYMBOL V DD HB HS V SS EPAD DESRIPTION Positive Supply to lower gate drivers. De-couple this pin to V SS. Bootstrap diode connected to HB. High-Side Bootstrap supply. External bootstrap capacitor is required. onnect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-Side Output. onnect to gate of High-Side power MOSFET. High-Side Source connection. onnect to source of High-Side power MOSFET. onnect negative side of bootstrap capacitor to this pin. High-Side input. Low-Side input. hip negative supply, generally will be ground. Low-Side Output. onnect to gate of Low-Side power MOSFET. Exposed Pad. onnect to ground or float. The EPAD is electrically isolated from all other pins. Timing Diagrams, t HPLH, t LPLH t HPHL, t LPHL, t MON t MOFF FIGURE 3. FIGURE 4. Typical Performance urves 0 0 I DDO, I HBO (ma) 0. T = +50 T = +25 T = +25 T = -40 I HBSO (ma) 0. T = +50 T = -40 T = +25 T = k 00k M FREQUEY (Hz) FIGURE 5. OPERATING URRENT vs FREQUEY 0.0 0k 00k M FREQUEY (Hz) FIGURE 6. HB TO V SS OPERATING URRENT vs FREQUEY FN4022 Rev 5.00 Page 6 of 3

7 Typical Performance urves (ontinued) V OHL, V OHH (mv) V HB = V DD = 9V V HB = V DD = 2V V HB = V DD = 4V V OLL, V OLH (mv) V HB = V DD = 9V V HB = V DD = 2V V HB = V DD = 4V TEMPERATURE ( ) FIGURE 7. GH LEVEL OUTPUT VOLTAGE vs TEMPERATURE TEMPERATURE ( ) FIGURE 8. W LEVEL OUTPUT VOLTAGE vs TEMPERATURE V HBR, V DDR (V) V DDR V HBR V HBH, V DDH (mv) V HBH V DDH TEMPERATURE ( ) TEMPERATURE ( ) FIGURE 9. UNDERVOLTAGE KOUT THRESLD vs TEMPERATURE FIGURE 0. UNDERVOLTAGE KOUT HYSTERESIS vs TEMPERATURE t LPLH, t LPHL, t HPLH, t HPHL (ns) t HPHL t HPLH t LPHL t LPLH I, I (A) TEMPERATURE ( ) FIGURE. PROPAGATION DELAYS vs TEMPERATURE V, V (V) FIGURE 2. PEAK PULLUP URRENT vs OUTPUT VOLTAGE FN4022 Rev 5.00 Page 7 of 3

8 Typical Performance urves (ontinued) I, I (A) FORWARD URRENT (A) V, V (V) FIGURE 3. PEAK PULLDOWN URRENT vs OUTPUT VOLTAGE FORWARD VOLTAGE (V) FIGURE 4. BOOTSTRAP DIODE I-V HARATERISTIS I DD, I HB (µa) I HB vs V HB I DD vs V DD V HS TO V SS VOLTAGE (V) V DD, V HB (V) V DD TO V SS VOLTAGE (V) FIGURE 5. QUIESENT URRENT vs VOLTAGE FIGURE 6. V HS VOLTAGE vs V DD VOLTAGE FN4022 Rev 5.00 Page 8 of 3

9 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION HANGE FN Updated Ordering Information Table on page. Added Revision History and About Intersil sections. Updated POD M8.5 from rev to rev 4. hanges since rev : Updated to new format by removing table, moving dimensions onto drawing and adding land pattern Typical Recommended Land Pattern, changed the following: 2.4(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) to 5.20(0.205) hanged Note "982" to "994" About Intersil Intersil orporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN4022 Rev 5.00 Page 9 of 3

10 Dual Flat No-Lead Plastic Package (DFN) Micro Lead Frame Plastic Package (MLFP) INDEX AREA 2X SEATING PLANE 7 2X INDEX AREA 0.5 E2 8 A B 4X 0 A E2/2 N D D 2 3 D/2 D/2 TOP VIEW SIDE VIEW N N- e 7 8 D2 (Nd-)Xe REF. 2 3 D2/2 BOTTOM VIEW L 2X 0.5 A3 4X P E/2 E/2 A2 NX k A E A A NX b M A B 9 // E B 0.0 2X B L2.4x4A 2 LEAD DUAL FLAT NO-LEAD PLASTI PAKAGE MILMETERS SYMBOL MIN NOMINAL MAX NOTES A A A A REF - b , 8 D 4.00 BS - D 3.75 BS - D , 8 E 4.00 BS - E 3.75 BS - E , 8 e 0.50 BS - k L N 2 2 Nd 6 3 P Rev. 0 8/03 NOTES:. Dimensioning and tolerancing conform to ASME Y4.5M N is the number of terminals. 3. Nd refer to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.5mm and 0.30mm from the terminal tip. 6. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PB Land Pattern Design efforts, see Intersil Technical Brief TB OMPANT TO JEDE MO-229-VGGD-2 ISSUE except for the L dimension. NX b 5 A L 5 TERMINAL TIP e FOR EVEN TERMINAL/SIDE FN4022 Rev 5.00 Page 0 of 3

11 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L6.5x5 6 LEAD QUAD FLAT NO-LEAD PLASTI PAKAGE (OMPANT TO JEDE MO-220VHHB ISSUE ) MILMETERS SYMBOL MIN NOMINAL MAX NOTES A A A A REF 9 b , 8 D 5.00 BS - D 4.75 BS 9 D , 8 E 5.00 BS - E 4.75 BS 9 E , 8 e 0.80 BS - k L L N 6 2 Nd 4 3 Ne P Rev. 2 0/02 NOTES:. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.5mm and 0.30mm from the terminal tip. 6. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PB Land Pattern Design efforts, see Intersil Technical Brief TB Features and dimensions A2, A3, D, E, P & are present when Anvil singulation method is used and not present for saw singulation. 0. Depending on the method of lead termination at the edge of the package, a maximum 0.5mm pull back (L) maybe present. L minus L to be equal to or greater than 0.3mm. FN4022 Rev 5.00 Page of 3

12 Package Outline Drawing M8.5 8 LEAD NARROW BODY SMALL OUTNE PLASTI PAKAGE Rev 4, /2 DETAIL "A".27 (0.050) 0.40 (0.06) INDEX AREA 4.00 (0.57) 3.80 (0.50) 6.20 (0.244) 5.80 (0.228) 0.50 (0.20) 0.25 (0.0) x TOP VIEW 8 0 SIDE VIEW B 0.25 (0.00) 0.9 (0.008) 2.20 (0.087) SEATING PLANE (0.97) 4.80 (0.89).75 (0.069).35 (0.053) (0.023).27 (0.050) (0.050) 0.5(0.020) 0.33(0.03) 0.25(0.00) 0.0(0.004) (0.205) SIDE VIEW A TYPIAL REOMMENDED LAND PATTERN NOTES:. Dimensioning and tolerancing per ANSI Y4.5M Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.00 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.024 inch). 7. ontrolling dimension: MILMETER. onverted inch dimensions are not necessarily exact. 8. This outline conforms to JEDE publication MS-02-AA ISSUE. FN4022 Rev 5.00 Page 2 of 3

13 Small Outline Exposed Pad Plastic Packages (EPSOI) N INDEX AREA 2 3 e D B 0.25(0.00) M A 2 3 N TOP VIEW SIDE VIEW P BOTTOM VIEW M E -B- -A- -- SEATING PLANE P A B S H 0.25(0.00) M B A 0.0(0.004) L M h x 45 M8.5 8 LEAD NARROW BODY SMALL OUTNE EXPOSED PAD PLASTI PAKAGE IHES MILMETERS SYMBOL MIN MAX MIN MAX NOTES A A B D E e BS.27 BS - H h L N P P Rev. 6/05 NOTES:. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y4.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.024 inch). 0. ontrolling dimension: MILMETER. onverted inch dimensions are not necessarily exact.. Dimensions P and P are thermal and/or electrical enhanced variations. Values shown are maximum size of exposed pad within lead count and body size. FN4022 Rev 5.00 Page 3 of 3