DATASHEET ISL Features. Applications. Related Literature. Ultra Low ON-Resistance, Low Voltage, Single Supply, SPDT Analog Switch

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1 DATASHEET ISL5453 Ultra Low ON-Resistance, Low Voltage, Single Supply, SPDT Analog Switch FN646 Rev. 3. The Intersil ISL5453 device is a low ON-resistance, low voltage, bidirectional, single pole/double throw (SPDT) analog switch designed to operate from a single +1.8V to +5.5V supply. Targeted applications include battery powered equipment which benefit from low r ON (.8 ) and fast switching speeds (t ON = 24ns, t OFF = 1ns). The digital logic input is 1.8V logic compatible when using a single +3.V supply. ell phones, for example, often face ASI functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to mux-in additional functionality while reducing ASI design risk. The ISL5453 is offered in the 6 Ld 1.2mmx1.mmx.5mm µtdfn and 6 Ld SOT-23 packages, alleviating board space limitations. The ISL5453 is a committed SPDT that consists of one normally open (NO) and one normally closed (N) switch. This configuration can also be used as a 2-to-1 multiplexer. TABLE 1. FEATURES AT A GLANE ISL5453 Number of Switches 1 SW SPDT or 2-1 MUX 1.8V r ON V t ON /t OFF 68ns/45ns 3V r ON 1.1 3V t ON /t OFF 29ns/12ns 5V r ON.8 5V t ON /t OFF Packages 24ns/1ns 6 Ld TDFN, 6 Ld SOT-23 Features Drop In replacement for the NLAS5123 ON-resistance (r ON ) - V = +5.V V = +3.V V = +1.8V r ON matching between channels r ON flatness (+4.5V supply) Single supply operation V to +5.5V Fast switching action (+4.5V supply) - t ON ns - t OFF ns Guaranteed break-before-make ESD HBM rating >6kV 1.8V MOS logic compatible (+3V supply) Available in 6 Ld µtdfn and 6Ld SOT-23 Packages Pb-free(RoHS compliant) Applications Battery powered, handheld, and portable equipment - ellular/mobile phones - Pagers - Laptops, notebooks, palmtops Portable test and measurement Medical equipment Audio and video switching Related Literature Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) FN646 Rev. 3. Page 1 of 12

2 Ordering Information PART NUMBER (Notes 1, 4) PART MARKG TEMP. RANGE ( ) PAKAGE (Pb-Free) ISL5453IRUZ-T(Note 2) -4 to Ld (.4mm pitch) 1.2x1.x.5 TDFN, Tape and Reel PKG. DWG. # L6.1.2x1.A ISL5453IHZ-T (Note 3) to Ld SOT-23, Tape and Reel MDP38 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 1% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD For Moisture Sensitivity Level (MSL), please see device information page for ISL5453. For more information on MSL please see techbrief TB363. Pin onfigurations (Note 5) ISL5453 (6 LD µtdfn) TOP VIEW Pin Descriptions P FUNTION System Power Supply Input (+1.8V to +5.5V) NO 1 6 Ground onnection N NO Digital ontrol Input Analog Switch ommon Pin Analog Switch Normally Open Pin N Analog Switch Normally losed Pin N NO ISL5453 (6 LD SOT-23) TOP VIEW NOTE: 5. Switches Shown for Logic Input Truth Table LOGI P N P NO On Off 1 Off On NOTE: Logic.5V. Logic 1 1.4V with a 2.V to 5.V supply. FN646 Rev. 3. Page 2 of 12

3 Absolute Maximum Ratings to V to 6.5V Input Voltages NO, N, (Note 6) to (() +.5V) Output Voltages (Note 6) to (() +.5V) ontinuous urrent NO, N, or mA Peak urrent NO, N, or (Pulsed 1ms, 1% Duty ycle, Max) mA ESD Rating Human Body Model >6kV Machine Model >2V harged Device Model >2.2kV Thermal Information Thermal Resistance (Typical) JA ( /W) J ( /W) 6 Ld µtdfn (Note 7) N/A 6 Ld SOT-23 (Notes 7, 8) Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +15 Pb-Free Reflow Profile see link below Operating onditions (Positive D Supply Voltage) V to 5.5V Analog Signal Range V to V (Digital Logic Input Voltage () V to Temperature Range to +85 AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. Signals on N, NO,, or exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. For J, the case temp location is taken at the package top center. Electrical Specifications - 5V Supply Test onditions: = +4.5V to +5.5V, = V, V H = 2.4V, V L =.8V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. PARAMETER TEST ONDITIONS ANALOG SWITH HARATERISTIS TEMP ( ) M (Notes 1, 11) TYP MAX (Notes 1, 11) UNITS Analog Signal Range, Full - V V ANALOG ON-Resistance, r ON = 4.5V, I = 1mA, V NO or V N = V to, (See Figure 5, Note 13) Full r ON Matching Between hannels, r ON r ON Flatness, r FLAT(ON) NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) ON Leakage urrent, I (ON) = 4.5V, I = 1mA, V NO or V N = 2.5V, (Note 13) = 4.5V, I = 1mA, V NO or V N = V to, (Notes 12, 13) = 5.5V, V =.3V, 5V, V NO or V N = 5V,.3V V = 5.5V, V =.3V, 5V, or V NO or V N =.3V, 5V, or floating DYNAMI HARATERISTIS Turn-ON Time, t ON = 4.5V, V NO or V N = 3.V, R L = 5, L = 35pF (See Figure 1, Note 13) Turn-OFF Time, t OFF = 4.5V, V NO or V N = 3.V, R L = 5, L = 35pF (See Figure 1, Note 13) Full Full na Full na na Full -3-3 na ns Full ns ns Full ns = 5.5V, V or V = 3.V, R = 5, Break-Before-Make Time Full ns Delay, t D NO N L L = 35pF (See Figure 3, Note 13) harge Injection, Q V G = V, R G =, L = 1.nF (See Figure 2) p OFF Isolation R L = 5, L = 5pF, f = 1kHz, V =1V RMS (See Figure 4) db rosstalk (hannel-to-hannel) R L = 5, L = 5pF, f = 1kHz, V =1V RMS (See Figure 6) db FN646 Rev. 3. Page 3 of 12

4 Electrical Specifications - 5V Supply Test onditions: = +4.5V to +5.5V, = V, V H = 2.4V, V L =.8V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. (ontinued) PARAMETER Total Harmonic Distortion f = 2Hz to 2kHz, V =.5V P-P, % R L =6-3dB Bandwidth R L = MHz NO or N OFF apacitance, OFF ON apacitance, (ON) = 4.5V, f = 1MHz, V NO or V N = V = V (See Figure 7) = 4.5V, f = 1MHz, V NO or V N = V = V (See Figure 7) pf pf POWER SUPPLY HARATERISTIS Power Supply Range Full V Positive Supply urrent, I+ = 5.5V, V = V or A Full A DIGITAL PUT HARATERISTIS Input Voltage Low, V L Full V Input Voltage High, V H Full V Input urrent, I H, I L = 5.5V, V = V or Full A Electrical Specifications - 3V Supply Test onditions: = +2.7V to +3.6V, = V, V H = 1.4V, V L =.5V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. PARAMETER TEST ONDITIONS TEMP ( ) M (Notes 1, 11) TYP MAX (Notes 1, 11) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON, ( TDFN) = 3.V, I = 1mA, V NO or V N = V to, (See Figure 5, Note 13) Full ON-Resistance, r ON, (SOT-23) = 3.V, I = 1mA, V NO or V N = V to, (See Figure 5, Note 13) Full r ON Matching Between hannels, r ON r ON Flatness, r FLAT(ON) = 3.V, I = 1mA, V NO or V N = 1.5V, (Note 13) = 3.V, I = 1mA, V NO or V N = V to, (Notes 12, 13) DYNAMI HARATERISTIS Turn-ON Time, t ON = 2.7V, V NO or V N = 1.5V, R L = 5, L = 35pF (See Figure 1, Note 13) Turn-OFF Time, t OFF = 2.7V, V NO or V N = 1.5V, R L = 5, L = 35pF (See Figure 1, Note 13) Full Full ns Full ns ns Full ns = 3.6V, V or V = 1.5V, R = 5, Break-Before-Make Time Delay, Full ns t D NO N L L = 35pF (See Figure 3, Note 13) harge Injection, Q V G = V, R G =, L = 1.nF (See Figure 2) p OFF Isolation R L = 5, L = 5pF, f = 1kHz, V =1V RMS (See Figure 4) db rosstalk (hannel-to-hannel) R L = 5, L = 5pF, f = 1kHz, V =1V RMS (See Figure 6) db Total Harmonic Distortion f = 2Hz to 2kHz, V =.5V P-P, % R L = 6-3dB Bandwidth R L = MHz NO or N OFF apacitance, OFF TEST ONDITIONS f = 1MHz, V NO or V N = V = V (See Figure 7) TEMP ( ) M (Notes 1, 11) TYP MAX (Notes 1, 11) UNITS pf FN646 Rev. 3. Page 4 of 12

5 Electrical Specifications - 3V Supply Test onditions: = +2.7V to +3.6V, = V, V H = 1.4V, V L =.5V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. (ontinued) PARAMETER ON apacitance, (ON) TEST ONDITIONS f = 1MHz, V NO or V N = V = V (See Figure 7) pf DIGITAL PUT HARATERISTIS Input Voltage Low, V L Full V Input Voltage High, V H Full V Input urrent, I H, I L = 3.6V, V = V or Full A Electrical Specifications - 1.8V Supply Test onditions: = +1.8V, = V, V H = 1V, V L =.4V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. PARAMETER TEST ONDITIONS ANALOG SWITH HARATERISTIS TEMP ( ) M (Notes 1, 11) TYP MAX (Notes 1, 11) UNITS Analog Signal Range, Full - V V ANALOG ON-Resistance, r ON = 1.8V, I = 1mA, V NO or V N = V to, (See Figure 5, Note 13) DYNAMI HARATERISTIS Turn-ON Time, t ON = 1.8V, V NO or V N = 1.5V, R L = 5, L = 35pF (See Figure 1, Note 13) Turn-OFF Time, t OFF = 1.8V, V NO or V N = 1.5V, R L = 5, L = 35pF (See Figure 1, Note 13) Break-Before-Make Time Delay, t D = 1.8V, V NO or V N = 1.5V, R L = 5, L = 35pF (See Figure 3, Note 13) Full ns Full ns ns Full ns Full ns harge Injection, Q V G =, R G = L = 1.nF (See Figure 2) p DIGITAL PUT HARATERISTIS Input Voltage Low, V L Full V Input Voltage High, V H Full V NOTES: 9. V = input voltage to perform proper function. 1. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 11. Parameters with M and/or MAX limits are 1% tested at +25, unless otherwise specified. Temperature limits established by characterization and are not production tested. 12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 13. Limits established by characterization and are not production tested. TEMP ( ) M (Notes 1, 11) TYP MAX (Notes 1, 11) UNITS FN646 Rev. 3. Page 5 of 12

6 Test ircuits and Waveforms LOGI PUT V H V L 5% t r < 2ns t f < 2ns SWITH PUT SWITH OUTPUT V Nx V t OFF 9% V OUT 9% SWITH PUT LOGI PUT NO OR N R L 5 V OUT L 35pF t ON Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POTS FIGURE 1. SWITHG TIMES Repeat test for all switches. L includes fixture and stray capacitance. R L V OUT = V (NO or N) R L + r ON FIGURE 1B. TEST IRUIT SWITH OUTPUT V OUT V OUT R G NO OR N V OUT LOGI PUT ON OFF ON V H V L V G L Q = V OUT x L LOGI PUT FIGURE 2A. MEASUREMENT POTS FIGURE 2. HARGE JETION FIGURE 2B. TEST IRUIT LOGI PUT V H V L V NX NO N R L 5 V OUT L 35pF SWITH OUTPUT V OUT V t D 9% LOGI PUT L includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POTS FIGURE 3B. TEST IRUIT FIGURE 3. BREAK-BEFORE-MAKE TIME FN646 Rev. 3. Page 6 of 12

7 Test ircuits and Waveforms (ontinued) SIGNAL GENERATOR NO OR N r ON = V 1 /1mA NO OR N V OR V NX 1mA V 1 V L OR V H ANALYZER R L FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE 5. r ON TEST IRUIT 5 NO OR N NO or N V OR 1 SIGNAL GENERATOR IMPEDANE ANALYZER V L OR V H ANALYZER R L N OR NO FIGURE 6. ROSSTALK TEST IRUIT FIGURE 7. APAITANE TEST IRUIT Detailed Description The ISL5453 is a bidirectional, single pole/double throw (SPDT) analog switch which offers precise switching capability from a single 1.8V to 5.5V supply with low ON-resistance (.8 ) and high speed operation (t ON = 24ns, t OFF = 1ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (5.5µW), low leakage currents (3nA max) and the small µtdfn and SOT-23 packages. The low on-resistance and r ON flatness provide very low insertion loss and distortion to application that require signal reproduction. Supply Sequencing and Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (see Figure 8). To prevent forward biasing these diodes, must be applied before any input signals, and the input signal voltages must remain between and. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low ron switch. onnecting schottky diodes to the signal pins (as shown in Figure 8) will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current. FN646 Rev. 3. Page 7 of 12

8 OPTIONAL SHOTTKY DIODE OPTIONAL PROTETION RESISTOR OPTIONAL SHOTTKY DIODE X V NX Power-Supply onsiderations The ISL5453 construction is typical of most single supply MOS analog switches, in that they have two supply pins: and. and drive the internal MOS switches and set their analog voltage limits. Unlike switches with a 4.5V maximum supply voltage, the ISL V maximum supply voltage provides plenty of room for the 1% tolerance of 4.3V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.8V but the part will operate with a supply below 1.8V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the Electrical Specifications tables starting on page 3 and Typical Performance urves on page 9 for details. and also power the internal logic and level shifters. The level shifters convert the input logic levels to switched and signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies because the input switching point becomes negative in this configuration. V FIGURE 8. OVERVOLTAGE PROTETION Logic-Level Thresholds This switch family is 1.8V MOS compatible (.5V and 1.4V) over a supply range of 2V to 5V (see Figure 15). At 5V the V IH level is about 1.2V. This is still below the 1.8V MOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. High-Frequency Performance In 5 systems, the ISL5453 has a -3dB bandwidth of 19MHz (see Figure 16). The frequency response is very consistent over a wide range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch s input to its output. Off isolation is the resistance to this feedthrough, while crosstalk indicates the amount of feedthrough from one switch to another. Figure 17 details the high off isolation and crosstalk rejection provided by this family. At 1kHz, off isolation is about 8dB in 5 systems, decreasing approximately 2dB per decade as frequency increases. Higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and or. FN646 Rev. 3. Page 8 of 12

9 Typical Performance urves T A = +25, Unless Otherwise Specified. r ON ( ) = 1.8V = 2.7V = 3V V (V) = 4.5V I = 1mA = 5V FIGURE 9. ON-RESISTANE vs SUPPLY VOLTAGE vs SWITH VOLTAGE r ON ( ) = 5V I = 1mA V (V) FIGURE 1. ON-RESISTANE vs SWITH VOLTAGE = 1.8V I = 1mA r ON ( ) = 3.V I = 1mA V (V) r ON ( ) V (V) FIGURE 11. ON-RESISTANE vs SWITH VOLTAGE FIGURE 12. ON-RESISTANE vs SWITH VOLTAGE t ON (ns) t OFF (ns) (V) FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE (V) FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE FN646 Rev. 3. Page 9 of 12

10 Typical Performance urves T A = +25, Unless Otherwise Specified. (ontinued) V H AND V L (V) V H V L NORMALIZED GA (db) GA (V) FIGURE 15. DIGITAL SWITHG POT vs SUPPLY VOLTAGE = 5.V R L = 5 V =.2V P-P to 2V P-P.1k.1k 1M 1M 1M FREQUENY (Hz) FIGURE 16. FREQUENY RESPONSE 1G -2 = 1.8V to 5.5V = 3.V 2 ROSSTALK (db) ISOLATION ROSSTALK OFF ISOLATION (db) Q (p) = 1.8V = 3.V = 5V k 1k 1k 1M 1M 1M 5M FREQUENY (Hz) FIGURE 17. ROSSTALK AND OFF ISOLATION V (V) FIGURE 18. HARGE JETION vs SWITH VOLTAGE Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: 57 PROESS: Submicron MOS FN646 Rev. 3. Page 1 of 12

11 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN) E A B L6.1.2x1.A 6 LEAD ULTRA TH DUAL FLAT NO-LEAD PLASTI PAKAGE P 1 REFERENE 2X.1 D MILLIMETERS SYMBOL M NOMAL MAX NOTES A X.1 A TOP VIEW A3.127 REF -.1 DETAIL A b D X.8 DETAIL B L1 A1 DETAIL A SIDE VIEW BOTTOM VIEW A3 A1 4X e A3 5X L A SEATG PLANE b 6X.1 A B.5 NOTE 3 DETAIL B P 1 LEAD.1x45 HAMFER E e.4 BS - L L N 6 2 Ne Rev. 2 8/6 NOTES: 1. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Ne refers to the number of terminals on E side. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between.15mm and.3mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is.5mm. 8. Maximum allowable burrs is.76mm in all directions. 9. JEDE Reference MO For additional information, to assist with the PB Land Pattern Design effort, see Intersil Technical Brief TB LAND PATTERN 1 FN646 Rev. 3. Page 11 of 12

12 SOT-23 Package Family D 2X 5 E1 SEATG PLANE.1 NX e N 1.15 A-B 2X (L1) A 6 2 e1 4 3 B.2 M A-B D b NX D 1 3 H E A1 D.2 2X A2 MDP38 SOT-23 PAKAGE FAMILY MILLIMETERS SYMBOL SOT23-5 SOT23-6 TOLERANE A MAX A1.1.1 ±.5 A ±.15 b.4.4 ±.5 c ±.6 D Basic E Basic E Basic e Basic e Basic L ±.1 L1.6.6 Reference N 5 6 Reference Rev. F 2/7 NOTES: 1. Plastic or metal protrusions of.25mm maximum per side are not included. 2. Plastic interlead protrusions of.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). 6. SOT23-5 version has no center lead (shown as a dashed line). A GAUGE PLANE.25 c L +3 - opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN646 Rev. 3. Page 12 of 12