DATASHEET ISL Features. Applications*(see page 16) Switches in the Signal Path

Transcription

1 DATASHEET ISL422 High-Speed USB 2.0 (480Mbps) Multiplexer with Overvoltage Protection (OVP) FN7627 Rev 0.00 The ISL422 is a single supply dual 2:1 multiplexer that can operate from a single 2.7V to.2v supply. It contains two SPDT (Single Pole/Double Throw) switches configured as a DPDT. The part was designed for switching or routing of USB High-Speed signals and/or USB Full-speed signals in portable battery powered products. The 6. switches were specifically designed to pass USB high speed/full speed data signals. They have high bandwidth and low capacitance to pass USB high speed data signals with minimal DISTORTION. The ISL422 has OVP circuitry on the D-/D+ OM pins that opens the USB in-line switches when the voltage at these pins exceeds 3.8V (typ) or goes negative by -0.V (typ). It isolates fault voltages up to +.2V or down to -V from getting passed to the other-side of the switch, thereby protecting the USB transceivers. The digital logic inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The ISL422 has an output enable pin to open all the switches. It can be used to facilitate proper bus disconnect and connection when switching between the USB sources. The ISL422 is available in 10 Ld 1.8mmx1.4mm µtqfn and 10 Ld TDFN packages. It operates over a temperature range of -40 to +8. Typical Application 3.3V Features High-Speed (480Mbps) and Full-Speed (12Mbps) Signaling apability per USB V Logic ompatible (2.7V to +3.6V Supply) Enable Pin to Open all Switches Low Power Mode Power OFF Protection D-/D+ Pins Overvoltage Protection for +.2V and -V Fault Voltages -3dB Frequency 780MHz Low ON 240MHz 3.3pF Low ON-Resistance 6. Single Supply Operation (V DD ) 2.7V to.2v Available in µtqfn and TDFN Packages Pb-Free (RoHS ompliant) ompliant with USB 2.0 Short ircuit and Overvoltage Requirements Without Additional External omponents Applications*(see page 16) MP3 and other Personal Media Players ellular/mobile Phones PDAs Digital ameras and amcorders USB Switching USB 2.0 HS Eye Pattern With Switches in the Signal Path 00Ω USB ONNETOR VDD VBUS D- D- OVP D+ D+ ISL422 LOGI ONTROL HSD1- HSD1+ HSD2- HSD2+ µp USB TRANSEIVER USB TRANSEIVER VOLTAGE SALE (0.1V/DIV) TIME SALE (0.2ns/DIV) FN7627 Rev 0.00 Page 1 of 18

2 Pin onfiguration ISL422 (10 LD 1.8X1.4 µtqfn) TOP VIEW ISL422 (10 LD 3X3 TDFN) TOP VIEW 8 HSD1+ 7 HSD1-6 D- 1 PD LOGI ONTROL 10 VDD VDD 9 10 LOGI ONTROL OVP 4 3 D+ HSD2- HSD HSD1+ 1 HSD2-2 HSD2+ D+ 4 7 HSD1- OVP 6 D- NOTE: 1. Switches Shown for = Logic 1 and = Logic 0. Pin Descriptions Truth Table µtqfn TDFN PIN NAME DESRIPTION HSD1-, HSD1+ HSD2-, HSD2+ STATE 1 2 HSD2- USB Data Port hannel HSD2+ USB Data Port hannel D+ USB Data OM Port 4 Ground onnection 6 D- USB Data OM Port 6 7 HSD1- USB Data Port hannel HSD1+ USB Data Port hannel ON OFF Normal 0 1 OFF ON Normal 1 0 OFF OFF Low Power 1 1 OFF OFF Normal Logic 0 when 0.V, Logic 1 when 1.4V with a 2.7V to 3.6V Supply. Note: In Low Power mode there is no persistence checking when in OVP condition. 8 9 Bus Switch Enable 9 10 VDD Power Supply 10 1 Select Logic ontrol Input - PD PD Thermal Pad. Tie to Ground or Float TABLE 1. USB - OVP POSSIBLE SITUATIONS AND TRIP POINT VOLTAGE TRIP POINT ODE SUPPLY SWITH SUPPLY (V DD ) OMs SHORTED TO PROTETED MIN MAX 2.7V to 3.3V 2.7V to.2v VBUS Yes 3.63V 3.9V 2.7V to 3.3V 2.7V to.2v -V Yes -0.76V -0.29V FN7627 Rev 0.00 Page 2 of 18

3 Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( ) PAKAGE (Pb-Free) PKG. DWG. # ISL422IRUZ-T (Notes 2, 3) U0-40 to Ld 1.8x1.4mm µtqfn (Tape and Reel) L10.1.8x1.4A ISL422IRUZ-T7A (Notes 2, 3) U0-40 to Ld 1.8x1.4mm µtqfn (Tape and Reel) L10.1.8x1.4A ISL422IRTZ (Note 4) to Ld 3x3 TDFN L10.3x3A ISL422IRTZ-T (Notes 2, 4) to Ld 3x3 TDFN (Tape and Reel) L10.3x3A ISL422IRTZEVAL1Z Evaluation Board NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD For Moisture Sensitivity Level (MSL), please see device information page for ISL422. For more information on MSL please see techbrief TB363. FN7627 Rev 0.00 Page 3 of 18

4 Absolute Maximum Ratings VDD to V to 6.V VDD to Dx V Dx to HSD1x, HSD2x V Input Voltages HSD2x, HSD1x V to 6.V, V to 6.V Output Voltages D+, D V to 6.V ontinuous urrent (HSD2x, HSD1x) ±40mA Peak urrent (HSD2x, HSD1x) (Pulsed 1ms, 10% Duty ycle, Max) ±100mA ESD Rating: Human Body Model (Tested per JESD22-A114-F)...>.kV Machine Model (Tested per JESD22-A11-A) >20V harged Device Model (Tested per JESD D).. >2kV Latch-up Tested per JEDE; lass II Level A..... at +8 Thermal Information Thermal Resistance (Typical) JA ( /W) J ( /W) 10 Ld µtqfn Package (Note 6, 7) Ld TDFN Package (Notes 8, 9) Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +10 Pb-Free Reflow Profile see link below Recommended Operating onditions Temperature Range to +8 V DD Supply Voltage Range V to.2v Logic ontrol Input Voltage V to.2v Analog Signal Range V DD = 2.7V to.2v V to 3.6V AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For J, the case temp location is taken at the package top center. 8. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB For J, the case temp location is the center of the exposed metal pad on the package underside. Electrical Specifications - 2.7V to.2v Supply Test onditions: V DD = +3.3V, = 0V, V H = 1.4V, V L = 0.V, V H =1.4V, V L = 0.V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40 to +8. PARAMETER ANALOG SWITH HARATERISTIS TEST ONDITIONS TEMP ( ) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS ON-Resistance, r ON (High-Speed) r ON Matching Between hannels, r ON (High-Speed) r ON Flatness, R FLAT(ON) (High-Speed) ON-Resistance, r ON OFF Leakage urrent, I HSD1x(OFF) ON Leakage urrent, I HSD1x(ON) V DD = 2.7V, = 0.V or 1.4V, =0.V, I Dx = 17mA, V HSD1x or V HSD2x = 0V to 400mV (see Figure 3, Note 1) V DD = 2.7V, = 0.V or 1.4V, =0.V, I Dx = 17mA, V HSD1x or V HSD2x = Voltage at max r ON, (Notes 14, 1) V DD = 2.7V, = 0.V or 1.4V, =0.V, I Dx = 17mA, V HSD1x or V HSD2x = 0V to 400mV, (Notes 13, 1) V DD = 3.3V, = 0.V or 1.4V, =0.V, I OMx = 17mA, V D+ or V D- = 3.3V (See Figure 4, Note 1) V DD =.2V, = V DD and = V DD or = 0V, V Dx = 0.3V, 3.3V, V HSD1x =3.3V, 0.3V, V HSD2x = 0.3V, 3.3V V DD =.2V, = = 0V, V Dx =0.3V, 3.3V, V HSD1X = 0.3V, 3.3V, V HSD2x = 3.3V, 0.3V Full Full Full Full na Full na µa Full µa OFF Leakage urrent, V DD =.2V, = = 0V or = V DD, I HSD2x(OFF) V Dx = 3.3V, 0.3V, V HSD2x = 0.3V, 3.3V, V HSD1X = 3.3V, 0.3V na Full na FN7627 Rev 0.00 Page 4 of 18

5 Electrical Specifications - 2.7V to.2v Supply Test onditions: V DD = +3.3V, = 0V, V H = 1.4V, V L = 0.V, V H =1.4V, V L = 0.V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40 to +8. (ontinued) PARAMETER ON Leakage urrent, I HSD2x(ON) TEST ONDITIONS V DD =.2V, = V DD, = 0V, V Dx = 0.3V, 3.3V, V HSD2x =0.3V, 3.3V, V HSD1x = 3.3V, 0.3V TEMP ( ) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS µa Full µa Power OFF Leakage urrent, I D+, I D- V DD = 0V, V D+ =.2V, V D- =.2V, 2-13 µa = = V DD Power OFF Logic urrent, V DD = 0V, = =.2V µa I, I Power OFF D+/D- urrent, I HSDX+, I HSDX- V DD = 0V, = = V DD, V HSDX+ =V HSDX- =.2V µa OVERVOLTAGE PROTETION DETETION Positive Fault-Protection Trip Threshold, V PFP Negative Fault-Protection Trip Threshold, V NFP OFF Persistence Time Fault Protection Response Time ON Persistence Time Fault Protection Recovery Time V DD = 2.7V to.2v, = 0V or V DD, = 0V See Table 1 on page 2 V DD = 2.7V to.2v, = 0V or V DD, = 0V See Table 1 on page 2 Negative OVP Response: V DD = 2.7V, = 0V or V DD, = 0V, V Dx = 0V to -V, R L = 1kΩ Positive OVP Response: V DD = 2.7V, = 0V or V DD, = 0V, V Dx = 0V to.2v, R L = 1kΩ V DD = 2.7V, = 0V or V DD, = 0V, V Dx = 0V to.2v or 0V to -V, R L = 1kΩ V V µs µs µs DYNAMI HARATERISTIS Turn-ON Time, t ON Turn-OFF Time, t OFF V DD = 3.3V, V INPUT = 3V, R L = 0, L = 0pF (see Figure 1) V DD = 3.3V, V INPUT = 3V, R L = 0, L = 0pF (see Figure 1) ns ns Break-Before-Make Time V DD = 3.3V, R L = 0Ω, L = 0pF (see Figure 2) ns Delay, t D Turn-ON Enable Time, t ENABLE Turn-OFF Disable Time, t DISABLE V DD = 3.3V, V INPUT = 3V, R L = 1k, L = 0pF, Time out of All-Off state V DD = 3.3V, V INPUT = 3V, R L = 1k, L = 0pF, Time into All-Off state, Time is highly dependent on the load (R L, L ) time constant ns ns Skew, (t SKEWOUT - t SKEWIN ) V DD = 3.3V, = 0V or 3.3V, = 0V, R L = 4, L =10pF, t R = t F = 00ps at 480Mbps, (Duty ycle = 0%) (see Figure 6) ps Rise/Fall Degradation (Propagation Delay), t PD V DD = 3.3V, = 0V or 3.3V, = 0V, R L = 4, L =10pF see Figure 6) ps rosstalk V DD = 3.3V, R L = 0, f = 240MHz (see Figure ) db OFF-Isolation V DD = 3.3V, = 3.3V, R L = 0, f = 240MHz db -3dB Bandwidth Signal = 0dBm, 0.2VD offset, R L = MHz OFF apacitance, HSxOFF f = 1MHz, V DD = 3.3V, = 0V or 3.3V, = V DD (see Figure 4) pf OM ON apacitance, DX(ON) f = 1MHz, V DD = 3.3V, = 0V or 3.3V, = 0V (see Figure 4) pf FN7627 Rev 0.00 Page of 18

6 Electrical Specifications - 2.7V to.2v Supply Test onditions: V DD = +3.3V, = 0V, V H = 1.4V, V L = 0.V, V H =1.4V, V L = 0.V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40 to +8. (ontinued) PARAMETER OM ON apacitance, DX(ON) TEST ONDITIONS f = 240MHz, V DD = 3.3V, = 0V or 3.3V, = 0V (see Figure 4) TEMP ( ) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS pf POWER SUPPLY HARATERISTIS Power Supply Range, V DD Full V Positive Supply urrent, I DD V DD =.2V, = 0V or V DD, = 0V µa Full µa Positive Supply urrent, I DD V DD = 3.6V, = 0V or V DD, = 0V µa Full µa Positive Supply urrent, I DD (Low Power State) V DD = 3.6V, = 0V, = V DD 2-6 µa Full µa Positive Supply urrent, I DD V DD = 4.3V, = 2.6V, = 0V or 2.6V µa Full µa Positive Supply urrent, I DD V DD = 3.6V, = 1.4V, = 0V or 1.4V µa DIGITAL INPUT HARATERISTIS Full µa Input Voltage Low, V L, V DD = 2.7V to 3.6V Full V V L Input Voltage High, V H, V DD = 2.7V to 3.6V Full V V H Input Voltage Low, V L, V DD = 3.7V to 4.2V Full V V L Input Voltage High, V H, V DD = 3.7V to 4.2 Full V V H Input Voltage Low, V L, V DD = 4.3V to.2v Full V V L Input Voltage High, V H, V DD = 4.3V to.2v Full V V H Input urrent, I L, I H V DD =.2V, = 0V, =.2V Full na Input urrent, I H V DD =.2V, =.2V, 4M pull-down resistor Full µa Input urrent, I L V DD =.2V, = 0V, 4M pull-up resistor Full µa NOTES: 10. V LOGI = Input voltage to perform proper function. 11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. Parameters with MIN and/or MAX limits are 100% tested at +2, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 14. r ON matching between channels is calculated by subtracting the channel with the highest max r ON value from the channel with lowest max r ON value, between HSD2+ and HSD2- or between HSD1+ and HSD Limits established by characterization and are not production tested. FN7627 Rev 0.00 Page 6 of 18

7 Test ircuits and Waveforms LOGI INPUT SWITH INPUT VDD 0V V INPUT 0% t OFF V OUT t r < 20ns t f < 20ns SWITH INPUT V INPUT V DD HSDxx Dx V OUT SWITH OUTPUT 0V 90% 90% VIN R L L t ON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. L includes fixture and stray capacitance. R L V OUT = V (INPUT) R L + r ON FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITHING TIMES FIGURE 1B. TEST IRUIT V DD LOGI INPUT SWITH OUTPUT V OUT VDD 0V 0V t D 90% V INPUT VIN HSD2x HSD1x Dx R L 0 V OUT L 10pF Repeat test for all switches. L includes fixture and stray capacitance. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST IRUIT FIGURE 2. BREAK-BEFORE-MAKE TIME V DD r ON = V 1 /17mA HSDx V HSDx V 1 0V OR VDD 17mA Dx Repeat test for all switches. FIGURE 3. r ON TEST IRUIT FN7627 Rev 0.00 Page 7 of 18

8 Test ircuits and Waveforms (ontinued) VDD VDD HSDxx SIGNAL GENERATOR HSD1x Dx 0 IMPEDANE ANALYZER Dx 0V OR VDD VIN ANALYZER Dx HSD2x N R L Repeat test for all switches. Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 4. APAITANE TEST IRUIT FIGURE. ROSSTALK TEST IRUIT VDD t ri 90% DIN+ DIN- 10% 90% 0% t skew_i 0% 10% t fitro DIN+ OUT+ 4 OUT- 4 DIN- VIN OMD2 OMD1 D2 D1 L L 90% OUT+ OUT- 10% 90% 0% 0% t skew_o tro - tri Delay Due to Switch for Rising Input and Rising Output Signals. tfo - tfi Delay Due to Switch for Falling Input and Falling Output Signals. t f0 10% tskew_0 hange in Skew through the Switch for Output Signals. tskew_i hange in Skew through the Switch for Input Signals. FIGURE 6A. MEASUREMENT POINTS FIGURE 6B. TEST IRUIT FIGURE 6. SKEW TEST FN7627 Rev 0.00 Page 8 of 18

9 Application Block Diagram 00 µontroller USB ONNETOR VBUS D- D+ ISL422 VDD VDD 4M LOGI IRUITRY D- D+ 4M OVP HSD1- HSD1+ HSD2- HSD2+ USB HIGH-SPEED OR FULL-SPEED TRANSEIVER #1 USB HIGH_SPEED OR FULL-SPEED TRANSEIVER #2 PORTABLE MEDIA DEVIE Detailed Description The ISL422 device is a dual single pole/double throw (SPDT) analog switch configured as a DPDT that operates from a single D power supply in the range of 2.7V to.2v. It was designed to function as a dual 2-to-1 multiplexer to select between two USB high-speed differential data signals in portable battery powered products. It is offered in a TDFN, and a small µtqfn packages for use in MP3 players, cameras, PDAs, cellphones, and other personal media players. The device has an enable pin to open all switches and put the part in a low power state. The part contains special overvoltage detection and protection (OVP) circuitry on the D-/D+ OM pins. This circuitry acts to open the USB in-line switches when the part senses a voltage on the OM pins that is >3.8V (typ) or < -0.V (typ). It isolates voltages up to.2v and down to -V from getting through to the other side of the switch to protect the USB transceivers connected at the signal pins (HSD1-, HSD1+, HSD2-, HSD2+). The part consists of four 6. high speed (HSx) switches. These switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. They can also swing from 0V to 3.6V to pass USB full speed (12Mbps) differential data signals with minimal distortion. The ISL422 was designed for MP3 players, cameras, cellphones, and other personal media player applications that have multiple high-speed or full-speed transceivers sections and need to multiplex between these USB sources to a single USB host (computer). A typical application block diagram of this functionality is previously shown. A detailed description of the HS switches is provided in the following section. High-Speed (HSx) Data Switches The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are bi-directional switches that can pass USB high-speed and USB full-speed signals when V DD is in the range of 2.7V to.2v. When powered with a 2.7V supply, these switches have a nominal r ON of 6. over the signal range of 0V to 400mV with a r ON flatness of 0.3. The r ON matching between the HSD1x switches and HSD2x switches over this signal range is only 0.2 ensuring minimal impact by the switches to USB high-speed signal transitions. As the signal level increases, the r ON switch resistance increases. At signal level of 3.3V, the switch resistance is nominally 12. See Figures 9, 10, 11, 12, 13, 14, 1 and 16 in the Typical Performance urves beginning on page 12. The HSx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high speed signal quality specifications. See Figure 21 in the Typical Performance urves on page 14 for USB High-speed Eye Pattern taken with switch in the signal path. The HSx switches can also pass USB full-speed signals (12Mbps) with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 22 in the Typical Performance urves on page 14 for USB Full-speed Eye Pattern taken with switch in the signal path. FN7627 Rev 0.00 Page 9 of 18

10 The HS1 channel switches are active (turned ON) whenever the voltage is logic 0 (Low) and the voltage is logic 0 (Low). The HS2 channel switches are active (turned ON) whenever the voltage is logic 1 (High) and the voltage is logic 0 (Low). OVERVOLTAGE PROTETION (OVP) The maximum normal operating signal range for the HSx switches is from 0V to 3.6V. For normal operation, the signal voltage should not be allowed to exceed these voltage levels or go below ground by more than -0.3V. However, in the event that a positive voltage > 3.8V (typ) to.2v, such as the USB V V BUS voltage, gets shorted to one or both of the OM+ and OM- pins or a negative voltage < -0.V (typ) to -V gets shorted to one or both of the OM pins, the ISL422 has OVP circuitry to detect the overvoltage condition and open the SPDT switches to prevent damage to the USB down-stream transceivers connected at the signal pins (HS1D-, HS1D+, HS2D-, HS2D+). The OVP and power-off protection circuitry allows the OM pins (D-, D+) to be driven up to.2v while the V DD supply voltage is in the range of 0V to.2v. In this condition, the part draws < 100µA of I OMx and I DD current and causes no stress to the I. In addition, the SPDT switches are OFF and the fault voltage is isolated from the other side of the switch. External V DD Series Resistor to Limit I DD urrent during Negative OVP ondition A 100Ω to 1kΩ resistor in series with the VDD pin (see Figure 7) is required to limit the IDD current draw from the system power supply rail during a negative OVP fault event. With a negative -V fault voltage at both OM pins, the graph in Figure 8 shows the IDD current draw for different external resistor values for supply voltages of 2.7V, 3.6V, and.2v. With a 00Ω resistor, the current draw is limited to around ma. When the negative fault voltage is removed, the I DD current will return to it s normal operation current of 2µA to 4µA. The series resistor also provides improved ESD and latch-up immunity. During an overvoltage transient event (such as occurs during system level IE ESD testing), substrate currents can be generated in the I that can trigger parasitic SR structures to turn ON, creating a low impedance path from the VDD power supply to ground. This will result in a significant amount of current flow in the I, which can potentially create a latch-up state or permanently damage the I. The external VDD resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. Under normal operation, the low microamp I DD current of the I produces an insignificant voltage drop across the series resistor resulting in no impact to switch operation or performance. I DD (ma) -V FAULT VOLTAGE D+ D- LOGI FIGURE 7. VDD SERIES RESISTOR TO LIMIT IDD URRENT DURING NEGATIVE OVP AND FOR ENHANED ESD AND LATH-UP IMMUNITY V.2V 3.6V PROTETION RESISTOR 100Ω to 1kΩ FIGURE 8. NEGATIVE OVP IDD URRENT vs RESISTOR VALUE vs V SUPPLY ISL422 Operation V SUPPLY OVP VDD I DD HSD1+ HSD2+ HSD1- HSD k RESISTOR (Ω) The following will discuss using the ISL422 shown in the Application Block Diagram on page 9. POWER The power supply connected at the VDD pin provides the D bias voltage required by the ISL422 part for proper operation. The ISL422 can be operated with a V DD voltage in the range of 2.7V to.2v. For lowest power consumption you should use the lowest V DD supply. A 0.01µF or 0.1µF decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. In a typical application, V DD will be in the range of 2.8V to 4.3V and will be connected to the battery or LDO of the portable media device. V OM+ = V OM- = -V FN7627 Rev 0.00 Page 10 of 18

11 LOGI ONTROL The state of the ISL422 device is determined by the voltage at the pin and the pin. is only active when the pin is logic 0 (Low). Refer to Truth Table on page 2. The ISL422 logic pins are designed to minimize current consumption when the logic control voltage is lower than the V DD supply voltage. With V DD = 3.6V and logic pins at 1.4V, the part typically draws only 2µA. With V DD = 4.3V and logic pins at 2.6V, the part typically draws only 3µA. Driving the logic pins to the V DD supply rail minimizes power consumption. The pin and pin have special circuitry that allows them to be driven with a voltage higher than the V DD supply voltage. These pins can be driven up to.2v with a V DD supply in the range of 2.7V to.2v. The pin is internally pulled low through 4M resistor to ground. The pin is internally pulled high through a 4M resistor to VDD. These pins can be tri-stated by a µprocessor or left floating. Logic ontrol Voltage Levels TABLE 2. LOGI ONTROL VOLTAGE LEVELS V DD SUPPLY RANGE LOGI = 0 (LOW) 2.7V to 3.6V 0.V 0.V or floating 3.7V to 4.2V 0.7V 0.7V or floating 4.3V to.2v 0.8V 0.8V or floating LOGI = 1 (HIGH) 1.4V or floating 1.7V or floating 2.0V or floating 1.4V 1.7V 2.0V HSD1 USB hannel If the pin = Logic 0 and the pin = Logic 0, high-speed hannel 1 will be ON. The HSD1- and HSD1+ switches are ON and the HSD2- and HSD2+ switches are OFF (high impedance). When a computer or USB hub is plugged into the common USB connector and hannel 1 is active, a link will be established between the USB 1 transceiver section of the media player and the computer. The device will be able to transmit and receive data from the computer. HSD2 USB hannel If the pin = Logic 1 and the pin = Logic 0, high-speed hannel 2 will be ON. The HSD2- and HSD2+ switches are ON and the HSD1- and HSD1+ switches are OFF (high impedance). When a USB cable from a computer or USB hub is connected at the common USB connector and the part has hannel 2 active, a link will be established between the USB 2 driver section of the media player and the computer. The device will be able to transmit and receive data from the computer. All Switches OFF Mode If the pin = Logic 0 and the pin = Logic 1, all of the switches will turn OFF (high impedance) and the part will be put in a low power mode. In this mode, the part draws only 10µA (max) of current across the operating temperature range. In the low power mode, the persistence checking of the OVP circuitry is de-activated. If the pin = Logic 1 and the pin = Logic 1, all of the switches will turn OFF (high impedance). In this state the complete OTV circuitry is activated. The all OFF state can be used to switch between the two USB sections of the media player. When disconnecting from one USB device to the other USB device, you can momentarily put the ISL422 switch in the all off state in order to get the computer to disconnect from the one device so it can properly connect to the other USB device when that channel is turned ON. Whenever the ISL422 senses a fault condition on the OM pins, all switches will be turned OFF regardless of the voltage levels at the and pins. USB 2.0 V BUS Short Requirements The USB specification in section states a USB device must be able to withstand a V BUS short (4.4V to.2v) or a -1V short to the D+ or D- signal lines when the device is either powered off or powered on for at least 24 hours. The ISL422 part has special power-off protection and OVP detection circuitry to meet these short circuit requirements. This circuitry allows the ISL422 to provide protection to the USB down-stream transceivers connected at its signal pins (HS1D-, HS1D+, HS2D-, HS2D+) to meet the USB specification short circuit requirements. The power-off protection and OVP circuitry allows the OM pins (D-, D+) to be driven up to.2v or down to -V while the V DD supply voltage is in the range of 0V to.2v. In these overvoltage conditions with a 00Ω external VDD resistor, the part draws < µa of current into the OM pins and causes no stress/damage to the I. In addition, all switches are OFF and the shorted V BUS voltage will be isolated from getting through to the other side of the switch channels, thereby protecting the USB transceivers. FN7627 Rev 0.00 Page 11 of 18

12 Typical Performance urves T A = +2, Unless Otherwise Specified I OM = 17mA I OM = 17mA V 6.3 r ON ( ) V 3.3V 3.6V 4.3V.2V V OM (V) FIGURE 9. ON-RESISTANE vs SUPPLY VOLTAGE vs SWITH VOLTAGE r ON ( ) V V OM (V) 2.7V 3.3V FIGURE 10. ON-RESISTANE vs SUPPLY VOLTAGE vs SWITH VOLTAGE 12 I OM = 17mA V +2 r ON ( ) 8 r ON ( ) 6 6.2V 4.3V V OM (V) FIGURE 11. ON-RESISTANE vs SUPPLY VOLTAGE vs SWITH VOLTAGE V DD = 2.7V I OM = 17mA V OM (V) FIGURE 12. ON-RESISTANE vs SWITH VOLTAGE 8 V DD = 3.3V I OM = 17mA +8 8 V DD = 4.3V I OM = 17mA r ON ( ) 6 +2 r ON ( ) V OM (V) FIGURE 13. ON-RESISTANE vs SWITH VOLTAGE V OM (V) FIGURE 14. ON-RESISTANE vs SWITH VOLTAGE FN7627 Rev 0.00 Page 12 of 18

13 Typical Performance urves T A = +2, Unless Otherwise Specified (ontinued) 30 2 V DD = 2.7V I OM = 17mA 18 1 V DD = 3.3V I OM = 17mA r ON (W) r ON (W) V OM (V) FIGURE 1. ON-RESISTANE vs SWITH VOLTAGE V OM (V) FIGURE 16. ON-RESISTANE vs SWITH VOLTAGE V INH AND V INL (V) TO V INH V INL V DD (V) FIGURE 17. DIGITAL SWITHING POINT vs SUPPLY VOLTAGE I DD URRENT (µa) = 0 OR 1 V DD =.2V 0 V DD = 3.3V LOGI VOLTAGE (V) FIGURE 18. I DD vs LOGI VOLTAGE vs V DD I DD URRENT (µa) 4 40 V DD = 3.3V 3 30 = 0 (NORMAL OPERATION) = 1 (LOW POWER) LOGI VOLTAGE (V) FIGURE 19. IDD vs LOGI VOLTAGE vs STATE I DD URRENT (µa) 700 V DD =.2V = 0 (NORMAL OPERATION) 0 = 1 (LOW POWER) LOGI VOLTAGE (V) FIGURE 20. IDD vs LOGI VOLTAGE vs STATE FN7627 Rev 0.00 Page 13 of 18

14 Typical Performance urves T A = +2, Unless Otherwise Specified (ontinued) V DD = 3.3V VOLTAGE SALE (0.1V/DIV) TIME SALE (0.2ns/DIV) FIGURE 21. EYE PATTERN: 480Mbps WITH USB SWITHES IN THE SIGNAL PATH V DD = 3.3V VOLTAGE SALE (0.V/DIV) TIME SALE (10ns/DIV) FIGURE 22. EYE PATTERN: 12Mbps WITH USB SWITHES IN THE SIGNAL PATH FN7627 Rev 0.00 Page 14 of 18

15 Typical Performance urves T A = +2, Unless Otherwise Specified (ontinued) NORMALIZED GAIN (db) NORMALIZED GAIN (db) R L = 0Ω V IN = 0dBm, 0.86VD BIAS 1M 10M 100M 1G FREQUENY (Hz) FIGURE 23. FREQUENY RESPONSE R L = 0Ω V IN = 0dBm, 0.2VD BIAS NORMALIZED GAIN (db) R L = 0Ω V IN = 0dBm, 0.2VD BIAS FREQUENY (MHz) FIGURE 24. OFF-ISOLATION Die haracteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): TRANSISTOR OUNT: 1297 PRSS: Submicron MOS FREQUENY (MHz) FIGURE 2. ROSSTALK FN7627 Rev 0.00 Page 1 of 18

16 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION HANGE 7/2/10 FN Initial Release. Products Intersil orporation is a leader in the design and manufacture of high-performance analog semiconductors. The ompany's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL422 To report errors or suggestions for this datasheet, please go to FITs are available from our website at opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN7627 Rev 0.00 Page 16 of 18

17 Package Outline Drawing L10.1.8x1.4A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTI PAKAGE Rev, 3/10 B A 6 PIN #1 ID X PIN 1 INDEX AREA X M 0.0 M 4 A B X TOP VIEW X 0.40 BOTTOM VIEW 4X 0.30 SEE DETAIL "X" 0.10 MAX. 0. (9 X 0.60) (10X 0.20) (0.70) SIDE VIEW SEATING PLANE 0.08 (4X 0.30) 8 (0.70) REF 6 7 (6X 0.40) PAKAGE OUTLINE TYPIAL REOMMENDED LAND PATTERN DETAIL "X" NOTES: Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.m Unless otherwise specified, tolerance : Decimal ± 0.0 Dimension applies to the metallized terminal and is measured between 0.1mm and 0.30mm from the terminal tip. JEDE reference MO-2. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7627 Rev 0.00 Page 17 of 18

18 Package Outline Drawing L10.3x3A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTI PAKAGE Rev, 3/10 B 3.00 A 6 PIN 1 INDEX AREA 6 PIN 1 INDEX AREA REF 8X 0.0 BS 10X (4X) M A 0.0 M B TOP VIEW X 0.2 ( 2.30 ) BOTTOM VIEW 0.80 MAX SEE DETAIL "X" 0.10 (2.90) (1.0) SEATING PLANE 0.08 SIDE VIEW (10 X 0.0) ( 8X 0.0 ) ( 10X 0.2 ) TYPIAL REOMMENDED LAND PATTERN NOTES: REF MIN MAX. DETAIL "X" Dimensions are in millimeters. Dimensions in ( ) for Reference Only Dimensioning and tolerancing conform to ASME Y14.m Unless otherwise specified, tolerance : Decimal ± 0.0 Angular ±2.0 Dimension applies to the metallized terminal and is measured between 0.1mm and 0.30mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. ompliant to JEDE MO-229-WEED-3 except exposed pad length (2.30mm). FN7627 Rev 0.00 Page 18 of 18