DATASHEET ISL Features. Applications. Related Literature. Pinouts (Note 1)

Transcription

1 DATASHEET ISL84781 Ultra Low ON-Resistance, Low-Voltage, Single Supply, 8-to-1 Analog Multiplexer FN605 Rev 4.00 The Intersil ISL84781 device contains precision, bidirectional, analog switches configured as an 8-channel multiplexer/demultiplexer. It is designed to operate from a single +1.6V to +3.6V supply. The device has an inhibit pin to simultaneously open all signal paths. ON-resistance is 0.4 with a +3. supply and 0.55 with a single +1.8V supply. Each switch can handle rail-to-rail analog signals. The off-leakage current is only 4nA max at +25 or 40nA max at +85 with a +3.3V supply. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL84781 is a 8-to-1 multiplexer device that is offered in a 16 Ld TSSOP package, and a 16 Ld thin QFN package. Table 1 summarizes the performance of this family. Related Literature TABLE 1. FEATURES AT A GLANE onfiguration ISL :1 Mux 3V r ON 3V t ON /t OFF 16ns/13ns 1.8V r ON V t ON /t OFF 24ns/16ns Packages 16 Ld TSSOP, 16 Ld 3x3 thin QFN Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches Features Pin ompatible Replacement for the MAX4781, and MAX4617 ON-resistance (r ON ) - = = +1.8V r ON Matching Between hannels r ON Flatness Across Signal Range Single Supply Operation V to +3.6V Low Power onsumption (PD) <0.2µW Fast Switching Action (V S = +3V) - t ON ns - t OFF ns Guaranteed Break-Before-Make High urrent Handling apacity (300mA ontinuous) Available in 16 Ld TSSOP and 16 Ld 3x3 Thin QFN 1.8V MOS-Logic ompatible (+3V Supply) Pb-Free (RoHS ompliant) ISL84781IR Replaces the ISL43L680IR. Applications Battery Powered, Handheld, and Portable Equipment - ellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops Portable Test and Measurement Medical Equipment Audio Switching and Routing Pinouts (Note 1) ISL84781 (16 LD TSSOP) TOP VIEW ISL84781 (16 LD 3x3 THIN QFN) TOP VIEW NO NO6 NO4 NO2 NO NO OM NO7 NO5 N LOGI NO1 NO0 NO3 ADD0 ADD1 OM NO7 NO NO1 NO0 NO3 ADD0 8 ADD N.. ADD2 ADD1 FN605 Rev 4.00 Page 1 of 12

2 Pinouts (Note 1) (ontinued) NOTE: 1. Switches Shown for Logic 0 Inputs. Truth Table ISL84781 ADD2 ADD1 ADD0 SWITH ON 1 X X X NONE NO NO NO NO NO NO NO NO7 NOTE: Logic 0 0.5V. Logic 1 1.4V, with a 3V supply. X = Don t are. Ordering Information PART NUMBER (Notes 2, 3, 4) PART MARKING TEMP. RANGE ( ) PAKAGE (Pb-free) PKG. DWG. # ISL84781IVZ IVZ -40 to Ld TSSOP M ISL84781IRZ 781Z -40 to Ld TQFN L16.3x3A 2. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications. 3. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 0% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD For Moisture Sensitivity Level (MSL), please see device information page for ISL For more information on MSL, please see Technical Brief TB363. Pin Descriptions PIN FUNTION System Power Supply Input (1.6V to 3.6V) N.. OM NO0 - NO7 ADD No onnect. Not internally connected. Ground onnection Digital ontrol Input. onnect to for Normal Operation. onnect to to turn all switches off. Analog Switch ommon Pin Analog Switch Input Pin Address Input Pin FN605 Rev 4.00 Page 2 of 12

3 Absolute Maximum Ratings to to 4.7V Input Voltages, NO, ADD (Note 5) to () + 0.3V Output Voltages OM (Note 5) to () + 0.3V ontinuous urrent NO or OM ±300mA Peak urrent NO or OM (Pulsed 1ms, % Duty ycle, Max) ±500mA ESD Rating Human Body Model >4kV Machine Model >30 harged Device Model >0 Thermal Information Thermal Resistance (Typical, Note 6) JA ( /W) 16 Ld TSSOP Package Ld 3x3 Thin QFN Package Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +150 Pb-Free Reflow Profile see link below Operating onditions Temperature Range to +85 AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Signals on NO, OM, ADD, or exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB37 for details. Electrical Specifications - 3V Supply Test onditions: V SUPPLY = +2.7V to +3.3V, =, V = 1.4V, V INL = 0.5V (Note 7), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40 to +85. PARAMETER TEST ONDITIONS TEMP ( ) MIN (Notes 8, 11) TYP MAX (Notes 8, 11) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0 - V ON-resistance, r ON = 2.7V, I OM = 0mA, V NO = V to, (See Figure 5) Full r ON Matching Between hannels, r ON = 2.7V, I OM = 0mA, V NO = Voltage at max r ON, (Note ) Full = 3.6V, V = V ADD = or (Note 12) r ON Flatness, R FLAT(ON) = 2.7V, I OM = 0mA, V NO = V to, (Note ) Full NO OFF Leakage urrent, I NO(OFF) = 3.3V, V OM = 0.3V, 3V, V NO = 3V, 0.3V na Full na OM ON Leakage urrent, = 3.3V, V OM = V NO = 0.3V, 3V na I OM(ON) Full na DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, Full µa I ADDL DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF Address Transition Time, t TRANS = 2.7V, V NO = V, R L = 50, L = 35pF, (See Figure 1, Note 12) = 2.7V, V NO = 1.5V, R L = 50, L = 35pF, (See Figure 1, Note 12) = 2.7V, V NO = 1.5V, R L = 50, L = 35pF, (See Figure 1, Note 12) ns Full ns ns Full ns ns Full ns Break-Before-Make Time, t BBM = 3.3V, V NO = 1.5V, R L = 50, L = 35pF, ns (See Figure 3, Note 12) Full ns harge Injection, Q L = 1.0nF, V G =, R G = 0, (See Figure 2) p Input OFF apacitance, OFF f = 1MHz, V NO = V OM =, (See Figure 6) pf FN605 Rev 4.00 Page 3 of 12

4 Electrical Specifications - 3V Supply Test onditions: V SUPPLY = +2.7V to +3.3V, =, V = 1.4V, V INL = 0.5V (Note 7), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40 to +85. (ontinued) TEMP MIN MAX PARAMETER TEST ONDITIONS ( ) (Notes 8, 11) TYP (Notes 8, 11) UNITS OM OFF apacitance, OFF f = 1MHz, V NO = V OM =, (See Figure 6) pf OM ON apacitance, OM(ON) f = 1MHz, V NO = V OM =, (See Figure 6) pf OFF-Isolation R L = 50, L = 35pF, f = 0kHz, (See Figure 4) db Total Harmonic Distortion (THD) f = 20Hz to 20kHz, 0.5V P-P, R L = % POWER SUPPLY HARATERISTIS Power Supply Range Full V Positive Supply urrent, I+ = 3.6V, V, V ADD = or, Switch On or Off µa Full µa NOTES: 7. V IN = Input voltage to perform proper function. 8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.. r ON matching between channels is calculated by subtracting the channel with the highest max r ON value from the channel with lowest max r ON value.. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 11. Parameters with MIN and/or MAX limits are 0% tested at +25, unless otherwise specified. Temperature limits established by characterization and are not production tested. 12. Limits established by characterization and are not production tested. Electrical Specifications: 1.8V Supply Test onditions: = +1.8V, =, V = 1V, V INL = 0.4V (Note 7), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40 to +85. PARAMETER TEST ONDITIONS TEMP ( ) MIN (Notes 8, 11) TYP MAX (Notes 8, 11) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0 - V ON-resistance, r ON = 1.8V, I OM =.0mA, V NO = 1., (See Figure 5) Full r ON Matching Between hannels, = 1.8V, I OM =.0mA, V NO = 1., r ON) (See Figure 5) Full r ON Flatness, R FLAT(ON) = 1.8V, I OM =.0mA, V NO =, 0.V, 1.6V, (See Figure 5) Full DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, Full A I ADDL ADD DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF Address Transition Time, t TRANS Break-Before-Make Time, t BBM = 1.8V, V NO = 1., R L = 50, L = 35pF, (See Figure 1, Note 12) = 1.8V, V NO = 1., R L = 50, L = 35pF, (See Figure 1, Note 12) = 1.8V, V NO = 1., R L = 50, L = 35pF, (See Figure 1, Note 12) = 1.8V, V NO = 1., R L = 50, L = 35pF, (See Figure 3, Note 12) ns Full ns ns Full ns ns Full ns ns harge Injection, Q L = 1.0nF, V G =, R G = 0 (See Figure 2) p FN605 Rev 4.00 Page 4 of 12

5 Test ircuits and Waveforms LOGI 50% t ON t r < 5ns t f < 5ns VNO0 NO0 NO1-NO7 OM SWITH OUTPUT VNO0 t OFF 0% 0% LOGI ADD2-0 R L 50 L 35pF Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. IBIT t ON /t OFF MEASUREMENT POINTS Repeat test for other switches. L includes fixture and stray capacitance. R L = V NOx R L + r ON FIGURE 1B. IBIT t ON /t OFF TEST IRUIT LOGI SWITH OUTPUT VNO0 VNO7 50% t TRANS t TRANS % t r < 5ns t f < 5ns 0% Logic input waveform is inverted for switches that have the opposite logic sense. VNO0 LOGI NO0 NO1-NO7 ADD2-0 OM R L 50 Repeat test for other switches. L includes fixture and stray capacitance. R L = V NOx R L + r ON L 35pF FIGURE 1. ADDRESS t TRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS t TRANS TEST IRUIT FIGURE 1. SWITHING TIMES LOGI SWITH OUTPUT OFF Q = x L ON OFF V G R G 0 NOx ADD2 ADD1 ADD0 HANNEL SELET OM LOGI L 00pF Repeat test for other switches. FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2B. Q TEST IRUIT FIGURE 2. HARGE INJETION FN605 Rev 4.00 Page 5 of 12

6 Test ircuits and Waveforms (ontinued) LOGI t r < 5ns t f < 5ns VNOx NO0-NO7 ADD2-0 OM R L 50 L 35pF SWITH OUTPUT 0% LOGI t BBM Repeat test for other switches. L includes fixture and stray capacitance. FIGURE 3A. t BBM MEASUREMENT POINTS FIGURE 3B. t BBM TEST IRUIT FIGURE 3. BREAK-BEFORE-MAKE TIME nf SIGNAL GENERATOR NOx r ON = V 1 /0mA NOx ANALYZER R L OM ADD2 ADD1 ADD0 OR HANNEL SELET OR V NX 0mA V 1 OM ADD2 ADD1 ADD0 OR HANNEL SELET Off-Isolation is measured between OM and Off NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded. FIGURE 4. OFF-ISOLATION TEST IRUIT FIGURE 5. r ON TEST IRUIT NOx 1MHz IMPEDANE ANALYZER OM ADD2 ADD1 ADD0 OR HANNEL SELET FIGURE 6. APAITANE TEST IRUIT FN605 Rev 4.00 Page 6 of 12

7 Detailed Description The ISL84781 analog multiplexer offers precise switching capability from a single 1.6V to 3.6V supply with ultra low ON-resistance (0.41 ) and high speed operation (t ON = 16ns, t OFF = 13ns) with +3V supply. The device is especially well-suited for portable battery powered equipment thanks to the low operating supply voltage (1.6V), low power consumption (0.2µW), and low leakage currents (70nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing and Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (See Figure 7). To prevent forward biasing these diodes, must be applied before any input signals, and the input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low r ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 7). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR FOR LOGI S 1k LOGI V NOx OPTIONAL PROTETION DIODE V OM OPTIONAL PROTETION DIODE FIGURE 7. OVERVOLTAGE PROTETION Power-Supply onsiderations The ISL84781 construction is typical of most single supply MOS analog multiplexers, in that it has two supply pins: and. and drive the internal MOS switches and set its analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL V maximum supply voltage provides plenty of room for the % tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance urves beginning on page 8 for details. and power the internal logic and level shifters. The level shifters convert the logic levels to switched and signals to drive the analog switch gate terminals. These multiplexers cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This device is 1.8V MOS compatible (0.5V and 1.4V) over a supply range of 2. to 3.6V (See Figure 12). At 3.6V the V IH level is about 1.27V. This is still below the 1.8V MOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. High-Frequency Performance In 50 systems, signal response is reasonably flat even past MHz with a -3dB bandwidth of 52MHz (See Figure 16). The frequency response is very consistent over a wide range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch s input to its output. Off-Isolation is the resistance to this feed-through. Figure 17 details the high Off Isolation provided by these devices. At 0kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. FN605 Rev 4.00 Page 7 of 12

8 Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and or. Typical Performance urves T A = +25, Unless Otherwise Specified = 1.65V I OM = 0mA = 3V I OM = 0mA r ON ( ) = 1.8V r ON ( ) = 2.7V 0.40 = 3V = 3.6V V OM (V) FIGURE 8. ON-RESISTANE vs SUPPLY VOLTAGE vs SWITH VOLTAGE V OM (V) FIGURE. ON-RESISTANE vs SWITH VOLTAGE r ON ( ) V OM (V) = 1.8V I OM = 0mA FIGURE. ON-RESISTANE vs SWITH VOLTAGE Q (p) = 1.8V V OM (V) = 3V FIGURE 11. HARGE INJETION vs SWITH VOLTAGE FN605 Rev 4.00 Page 8 of 12

9 Typical Performance urves T A = +25, Unless Otherwise Specified (ontinued) V AND V INL (V) V V INL t RANS (ns) (V) FIGURE 12. DIGITAL SWITHING POINT vs SUPPLY VOLTAGE (V) FIGURE 13. ADDRESS TRANS TIME vs SUPPLY VOLTAGE t ON (ns) t OFF (ns) NORMALIZED GAIN (db) (V) FIGURE 14. IBIT TURN-ON TIME vs SUPPLY VOLTAGE = 3V 0 GAIN - PHASE R L = 50 V IN = 0.2V P-P to 2V P-P FREQUENY (MHz) FIGURE 16. FREQUENY RESPONSE PHASE ( ) (V) FIGURE 15. IBIT TURN-OFF TIME vs SUPPLY VOLTAGE OFF ISOLATION (db) 0 = 3V ISOLATION k k 0k 1M M 0M 500M FREQUENY (Hz) FIGURE 17. OFF-ISOLATION Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): (QFN Paddle onnection: To Ground or Float) TRANSISTOR OUNT: 228 PROESS: Submicron MOS FN605 Rev 4.00 Page of 12

10 opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN605 Rev 4.00 Page of 12

11 Package Outline Drawing M LEAD THIN SHRINK SMALL OUTLINE PAKAGE (TSSOP) Rev 2, 5/ A ±0. 16 SEE DETAIL "X" ± PIN #1 I.D. MARK 0.20 B A B TOP VIEW END VIEW H REF SEATING PLANE 0. SIDE VIEW 1.20 MAX / M B A / MIN 0.15 MAX DETAIL "X" GAUGE PLANE ± (1.45) NOTES: (5.65) (0.65 TYP) (0.35 TYP) TYPIAL REOMMENDED LAND PATTERN Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y14.5M-14. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. Dimension in ( ) are for reference only. onforms to JEDE MO-153. FN605 Rev 4.00 Page 11 of 12

12 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) ) 6 INDEX AREA A 4X X 0.15 B 2X 0.15 A SEATING PLANE 4X P (DATUM B) (DATUM A) 6 INDEX AREA 4X P NX L 8 L N N e D D1 D2 D2 2 D/2 D1/2 TOP VIEW SIDE VIEW NX b (Nd-1)Xe REF. N NX b E1/2 E/2 A 0. M A B SETION "-" e TERMINAL TIP FOR ODD TERMINAL/SIDE 5 BOTTOM VIEW 5 L1 7 L 2X 0.15 A A3 NX k A2 8 E2/2 A1 E2 A1 E1 7 8 E B 2X 0.15 B 0.08 (Ne-1)Xe REF. L / / ORNER OPTION 4X 0. e L1 L FOR EVEN TERMINAL/SIDE L16.3x3A 16 LEAD THIN QUAD FLAT NO-LEAD PLASTI PAKAGE MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A A A A REF b , 8 D 3.00 BS - D BS D , 8, E 3.00 BS - E BS E , 8, e 0.50 BS - k L N 16 2 Nd 4 3 Ne 4 3 P Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PB Land Pattern Design efforts, see Intersil Technical Brief TB38.. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.. ompliant to JEDE MO-220WEED-2 Issue, except for the E2 and D2 MAX dimension. FN605 Rev 4.00 Page 12 of 12