ISL84051, ISL84052, ISL84053

Transcription

1 Data Sheet FN Low Voltage, Single and Dual Supply, 8 to 1 Multiplexer, Dual 4 to 1 Multiplexer and a Triple SPDT Analog Switch The Intersil devices are precision, bidirectional, analog switches configured as a 8-hannel multiplexer/demultiplexer (ISL84051), a dual differential 4-hannel multiplexer/demultiplexer (ISL84052) and a triple single pole/double throw (SPDT) switch (ISL84053) designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. All devices have an inhibit pin to simultaneously open all signal paths. ON-resistance is 60Ω with a ±5V supply and 125Ω with a single +5V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 0.1nA at +25 or 5nA at +85 with a ±5V supply. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/MOS logic compatibility when using a single +3.3V and +5V supply or dual ±5V supplies. The ISL84051 is a 8-to-1 multiplexer device. The ISL84052 is a dual 4-to-1 multiplexer device. The ISL84053 is a committed triple SPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANE ONFIGURATION Related Literature ISL84051 ISL84052 ISL :1 Mux DUAL 4:1 Mux TRIPLE SPDT ±5V r ON 60Ω 60Ω 60Ω ±5V t ON /t OFF 50ns/40ns 50ns/40ns 50ns/40ns 5V r ON 125Ω 125Ω 125Ω 5V t ON /t OFF 90ns/60ns 90ns/60ns 90ns/60ns 3V r ON 250Ω 250Ω 250Ω 3V t ON /t OFF 180ns/ns 180ns/ns 180ns/ns Packages 16 Ld SOI 16 Ld QSOP 16 Ld TSSOP 16 Ld SOI 16 Ld QSOP 16 Ld TSSOP 16 Ld SOI 16 Ld QSOP Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches Features Drop-in Replacements for MAX4051/MAX4051A, MAX4052/MAX4052A and MAX4053/MAX4053A Pin ompatible with MAX4581, MAX4582, MAX4583 and with Industry Standard 74H4051, 74H4052 and 74H4053 ON-Resistance (r ON ) Max, V S = ±5V Ω ON-Resistance (r ON ) Max, V S = +3V Ω r ON Matching Between hannels <6Ω Low harge Injection p (Max) Single Supply Operation V to +12V Dual Supply Operation ±2V to ±6 Fast Switching Action (V S = +5V) - t ON ns - t OFF ns Guaranteed Max V S = ±5V nA Guaranteed Break-Before-Make TTL, MOS ompatible Pb-Free Available (RoHS ompliant) Applications Portable Equipment ommunications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems Test Equipment - Medical Ultrasound - Magnetic Resonance Image - T and PET Scanners (MRI) - ATE - Electrocardiograph Audio and Video Signal Routing Various ircuits - +3V/+5V DAs and ADs - Sample and Hold ircuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset ircuits 1 AUTION: These devices are sensitive to electrostatic discharge; follow proper I Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. opyright Intersil Americas Inc , All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

2 Pinouts ISL84051 (16 LD SOI, QSOP, TSSOP) TOP VIEW ISL84052 (16 LD SOI, QSOP, TSSOP) TOP VIEW NO NO0B 1 16 NO NO2 NO1B 2 15 NO1A 3 14 NO4 B 3 14 NO2A NO NO0 NO3B 4 13 A NO NO6 NO2B 5 12 NO0A 6 11 ADD 6 11 NO3A ADDB ADDA ADDB ADDA ISL84053 (16 LD SOI, QSOP) TOP VIEW NOB 1 16 NB 2 15 B NOA 3 14 A 4 13 NO NA 5 12 N 6 11 ADD 7 10 ADDB 8 9 ADDA NOTE: 1. Switches Shown for Logic 0 Inputs. 2 FN6047.8

3 Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( ) PAKAGE PKG. DWG. # ISL84051IB* 84051IB -40 to Ld SOI M16.15 ISL84051IBZ* (Note) 84051IBZ -40 to Ld SOI (Pb-free) M16.15 ISL84051IA* IA -40 to Ld QSOP M16.15A ISL84051IAZ* (Note) ISL84051IVZ* (Note) IAZ -40 to Ld QSOP (Pb-free) IVZ -40 to Ld TSSOP (Pb-free) M16.15A M ISL84052IB* 84052IB -40 to Ld SOI M16.15 ISL84052IBZ* (Note) 84052IBZ -40 to Ld SOI (Pb-free) M16.15 ISL84052IA* IA -40 to Ld QSOP M16.15A ISL84052IAZ* (Note) ISL84052IVZ* (Note) IAZ -40 to Ld QSOP (Pb-free) IVZ -40 to Ld TSSOP (Pb-free) M16.15A M ISL84053IB* 84053IB -40 to Ld SOI M16.15 ISL84053IBZ* (Note) 84053IBZ -40 to Ld SOI (Pb-free) M16.15 ISL84053IA* IA -40 to Ld QSOP M16.15A ISL84053IAZ* (Note) IAZ -40 to Ld QSOP (Pb-free) M16.15A *Add -T suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-020. Pin Description PIN FUNTION Positive Power Supply Input Negative Power Supply Input. onnect to for Single Supply onfigurations. Ground onnection Truth Tables ISL84051 ADD ADDB ADDA SWITH ON 1 X X X None NO NO NO NO NO NO NO NO7 ISL84052 ADDB ADDA SWITH ON 1 X X None NO NO NO NO3 ISL84053 ADD ADD B ADD A SWITH ON 1 X X X None 0 X X 0 N A 0 X X 1 NO A 0 X 0 X N B 0 X 1 X NO B 0 0 X X N 0 1 X X NO NOTE: Logic 0 0.8V. Logic 1 2.4V, with between 2.7V and 10V. X = Don t are. NO N ADD Digital ontrol Input. onnect to for Normal Operation. onnect to to turn all switches off. Analog Switch ommon Pin Analog Switch Normally Open Pin Analog Switch Normally losed Pin Address Input Pin 3 FN6047.8

4 Absolute Maximum Ratings to V to 15V to V to 15V to V to 0.3V Input Voltages, NO, N, ADD (Note 2) (() - 0.3) to (() + 0.3V) Output Voltages (Note 2) (() - 0.3) to (() + 0.3V) ontinuous urrent (Any Terminal) ±30mA Peak urrent NO, N, or (Pulsed 1ms, 10% Duty ycle, Max) ±ma ESD Rating HBM (Per MIL-STD-883, Method ) >2kV Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( /W) 16 Ld SOI Package Ld QSOP Package Ld TSSOP Package Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +150 Pb-free reflow profile see link below Operating onditions Temperature Range ISL8405x to +85 AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 2. Signals on N, NO,, ADD, or exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 5V Supply Test onditions: V SUPPLY = ±4.5V to ±5.5V, = 0V, V = 2.4V, V INL = 0.8V (Note 4), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON V S = ±5V, I = 1mA, V NO or V N = ±3V (see Figure 5) Ω Full Ω r ON Matching Between hannels, V S = ±5V, I = 1mA, V NO or V N = ±3V (Note 7) Ω Δr ON Full Ω r ON Flatness, r FLAT(ON) NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OFF Leakage urrent, I (OFF), (ISL84051) OFF Leakage urrent, I (OFF), (ISL84052, ISL84053) ON Leakage urrent, I (ON), (ISL84051) V S = ±5V, I = 1mA, V NO or V N = ±3V, 0V (Note 8) V S = ±5.5V, V = ±4.5V, V NO or V N = ±4.5V V S = ±5.5V, V = ±4.5V, V NO or V N = ±4.5V V S = ±5.5V, V = ±4.5V, V NO or V N = ±4.5V V S = ±5.5V, V = V NO or V N = ±4.5V Ω Full Ω na Full -5-5 na na Full -5-5 na na Full na na Full -5-5 na ON Leakage urrent, I (ON), (ISL84052, ISL84053) V S = ±5.5V, V = V NO or V N = ±4.5V na Full na DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, V S = ±5.5V, V, V ADD = 0V or Full µa I ADDL 4 FN6047.8

5 Electrical Specifications - 5V Supply Test onditions: V SUPPLY = ±4.5V to ±5.5V, = 0V, V = 2.4V, V INL = 0.8V (Note 4), Unless Otherwise Specified (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON V S = ±4.5V, V NO or V N = ±3V, = 300Ω, L = 35pF, V IN = 0V to 3V (see Figure 1) Inhibit Turn-OFF Time, t OFF V S = ±4.5V, V NO or V N = ±3V, = 300Ω, L = 35pF, V IN = 0V to 3V (see Figure 1) Address Transition Time, t TRANS V S = ±4.5V, V NO or V N = ±3V, = 300Ω, L = 35pF, V IN = 0V to 3V (see Figure 1) Break-Before-Make Time, t BBM V S = ±5.5V, V NO or V N = 3V, = 300Ω, L = 35pF, V IN = 0V to 3V (see Figure 3) ns Full ns ns Full ns ns ns harge Injection, Q L = 1.0nF, V G = 0V, R G = 0Ω (see Figure 2) p NO/N OFF-apacitance, OFF f = 1MHz, V NO or V N = V = 0V (see Figure 7) pf OFF-apacitance, OFF ON-apacitance, (ON) f = 1MHz, V NO or V N = V = 0V (see Figure 7) f = 1MHz, V NO or V N = V = 0V (see Figure 7) ISL pf ISL pf ISL pf ISL pf ISL pf ISL pf OFF Isolation rosstalk, (ISL84052, ISL84053 Only) = 50Ω, L = 15pF, f = khz V NO or V N = 1V RMS (see Figures 4 and 6) <90 - db < db POWER SUPPLY HARATERISTIS Power Supply Range Full ±2 - ±6 V Positive Supply urrent, I+ V S = ±5.5V, V, V ADD = 0V or, Switch On or Off µa Full µa Negative Supply urrent, I µa Full µa Electrical Specifications: 5V Supply Test onditions: = +4.5V to +5.5V, = = 0V, V = 2.4V, V INL = 0.8V (Note 4), Unless Otherwise Specified. PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNIT S ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0 - V ON-Resistance, r ON = 5V, I = 1.0mA, V NO or V N = 3.5V (see Figure 5) Ω Full Ω NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OFF Leakage urrent, I (OFF), (ISL84051) OFF Leakage urrent, I (OFF), (ISL84052, ISL84053) = 5.5V, V = 0V, 4.5V, V NO or V N = 4.5V, 0V = 5.5V, V = 0V, 4.5V, V NO or V N = 4.5V, 0V = 5.5V, V = 0V, 4.5V, V NO or V N = 4.5V, 0V na Full na na Full na na Full -5-5 na 5 FN6047.8

6 Electrical Specifications: 5V Supply Test onditions: = +4.5V to +5.5V, = = 0V, V = 2.4V, V INL = 0.8V (Note 4), Unless Otherwise Specified. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNIT S ON Leakage urrent, = 5.5V, V = V NO or V N = 4.5V na I (ON) Full na DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, = 5.5V, V, V ADD = 0V or Full µa I ADDL DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON = 4.5V, V NO or V N = 3V, = 300Ω, L = 35pF, V IN = 0 to 3V (see Figure 1) Inhibit Turn-OFF Time, t OFF = 4.5V, V NO or V N = 3V, = 300Ω, L = 35pF, V IN = 0V to 3V (see Figure 1) Break-Before-Make Time, t BBM = 5.5V, V NO or V N = 3V, = 300Ω, L = 35pF, V IN = 0V to 3V (see Figure 3) ns Full ns ns Full ns ns harge Injection, Q L = 1.0nF, V G = 0V, R G = 0Ω (see Figure 2) p OFF Isolation rosstalk, (Note 10) (ISL84052, ISL Only) = 50Ω, L = 15pF, f = khz V NO or V N =1V RMS (see Figures 4 and 6) <90 - db <-90 - db POWER SUPPLY HARATERISTIS Power Supply Range Full 2-12 V Positive Supply urrent, I+ = 5.5V, = 0V, V, V ADD = 0V or, Switch On or Off µa Full µa Electrical Specifications: 3.3V Supply Test onditions: = +3.0V to +3.6V, = = 0V, V = 2.4V, V INL = 0.8V (Note 4), Unless Otherwise Specified. PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0 - V ON-Resistance, r ON = 3V, I = 1.0mA, V NO or V N = 1.5V Ω Full Ω NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OFF Leakage urrent, I (OFF), (ISL84051) OFF Leakage urrent, I (OFF), (ISL84052, ISL84053) = 3.6V, V = 0V, 3V, V NO or V N = 3V, 0V = 3.6V, V = 0V, 3V, V NO or V N = 3V, 0V = 3.6V, V = 0V, 3V, V NO or V N = 3V, 0V na Full na na Full na na Full -5-5 na ON Leakage urrent, = 3.6V, V = V NO or V N = 3V na I (ON) Full na 6 FN6047.8

7 Electrical Specifications: 3.3V Supply Test onditions: = +3.0V to +3.6V, = = 0V, V = 2.4V, V INL = 0.8V (Note 4), Unless Otherwise Specified. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, = 3.6V, V, V ADD = 0V or Full µa I ADDL DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF = 3V, V NO or V N = 1.5V, = 300Ω, L = 35pF, V IN = 0V to 3V (see Figure 1) = 3V, V NO or V N = 1.5V, = 300Ω, L = 35pF, V IN = 0V to 3V (see Figure 1) ns Full ns ns Full ns Break-Before-Make Time, t BBM = 3.6V, V NO or V N = 1.5V, = 300Ω, L =35pF, V IN = 0V to 3V (see Figure 3) ns harge Injection, Q L = 1.0nF, V G = 0V, R G = 0Ω (see Figure 2) p OFF Isolation rosstalk, (Note 10) (ISL84052, ISL84053 Only) = 50Ω, L = 15pF, f = khz V NO or V N = 1V RMS, (see Figures 4 and 6) <90 - db <-90 - db POWER SUPPLY HARATERISTIS Power Supply Range Full 2-12 V Positive Supply urrent, I+ = 3.6V, = 0V, V, V ADD = 0V or Switch On or Off µa Full µa NOTES: 4. V IN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are % tested at +25. Over-temperature limits established by characterization and are not production tested. 7. Δr ON = r ON (MAX) - r ON (MIN). 8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 9. Leakage parameter is % tested at high temp, and guaranteed by correlation at Between any two switches. 7 FN6047.8

8 Test ircuits and Waveforms NO0 NO1-NO7 ISL84051 ADDA- 300Ω L 35pF 3V 0V 50% t ON t r < 20ns t f < 20ns NO0 NO1-NO3 ISL84052 SWITH OUTPUT 0V t OFF 90% 90% ADDA-B 300Ω L 35pF Logic input waveform is inverted for switches that have the opposite logic sense. N X NO X ISL84053 X ADD X 300Ω L 35pF Repeat test for other switches. L includes fixture and stray capacitance. = V (NO or N) + r ON FIGURE 1A. IBIT t ON /t OFF MEASUREMENT POINTS FIGURE 1B. IBIT t ON /t OFF TEST IRUIT FIGURE 1. SWITHING TIMES 8 FN6047.8

9 Test ircuits and Waveforms (ontinued) NO0 NO7 NO1-NO6 ISL84051 ADDA- 300Ω L 35pF 3V 0V 50% t TRANS t r < 20ns t f < 20ns NO0 NO3 NO1-NO2 ISL84052 SWITH OUTPUT VNOX 0V 90% ADDA-B 300Ω L 35pF VNOX 10% t TRANS Logic input waveform is inverted for switches that have the opposite logic sense. N X NO X ISL84053 X ADD X 300Ω L 35pF Repeat test for other switches. L includes fixture and stray capacitance. = V (NO or N) + r ON FIGURE 1. ADDRESS t TRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS t TRANS TEST IRUIT FIGURE 1. SWITHING TIMES (ontinued) 9 FN6047.8

10 Test ircuits and Waveforms (ontinued) SWITH OUTPUT OFF ON OFF Δ 3V 0V V G R G 0Ω NO or N ADDX L 1nF Q = Δ x L Repeat test for other switches. FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2B. Q TEST IRUIT FIGURE 2. HARGE INJETION NO0-NO7 ADDA- 300Ω L 35pF ISL V 0V t r < 20ns t f < 20ns NO0-NO3 SWITH OUTPUT 0V t BBM 80% ADDA-B ISL Ω L 35pF NO X N X ISL84053 X L 300Ω 35pF ADD X Repeat test for other switches. L includes fixture and stray capacitance. FIGURE 3A. t BBM MEASUREMENT POINTS FIGURE 3B. t BBM TEST IRUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 10 FN6047.8

11 Test ircuits and Waveforms (ontinued) SIGNAL GENERATOR NO or N V NO or N ADDX 0V OR ADDX 0V OR ANALYZER 0V OR FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE 5. r ON TEST IRUIT FIGURE 6. ROSSTALK TEST IRUIT FIGURE 7. APAITANE TEST IRUIT 11 FN6047.8

12 Detailed Description The analog switches offer precise switching capability from a bipolar ±2V to ±6V or a single 2V to 12V supply with low on-resistance (60Ω) and high speed operation (t ON = 50ns, t OFF = 40ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (3μW), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (see Figure 8). To prevent forward biasing these diodes, and must be applied before any input signals, and input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low r ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR FOR S 1kΩ V NO OR N FIGURE 8. OVERVOLTAGE PROTETION OPTIONAL PROTETION DIODE V OPTIONAL PROTETION DIODE Power-Supply onsiderations The ISL8405x construction is typical of most MOS analog switches, in that they have three supply pins:,, and. and drive the internal MOS switches and set their analog voltage limits, so there are no connections between the analog signal path and. Unlike switches with a 13V maximum supply voltage, the ISL8405x 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies. The minimum recommended supply voltage is 2V or ±2V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the Electrical Specification tables beginning on page 4 and Typical Performance urves beginning on page 13 for details. and power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched and signals to drive the analog switch gate terminals. Logic-Level Thresholds and power the internal logic stages, so has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a supply range of 2.7V to 10V. At 12V the V IH level is about 3.5V. This is still below the MOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a V OH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past MHz (see Figure 17). Figure 17 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch s input to its output. Off isolation is the resistance to this feed through, while crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high off isolation and crosstalk rejection provided by this family. At 10MHz, off isolation is about 55dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. 12 FN6047.8

13 Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and. Typical Performance urves T A = +25, Unless Otherwise Specified r ON (Ω) = -5V = 0V V = () - 1V I = 1mA (V) r ON (Ω) I = 1mA +25 = 2.7V -40 = 0V = 0V 90 = 5V = 0V V (V) FIGURE 9. ON-RESISTANE vs SUPPLY VOLTAGE FIGURE 10. ON-RESISTANE vs SWITH VOLTAGE FIGURE 11. ON-RESISTANE vs SWITH VOLTAGE FIGURE 12. HARGE INJETION vs SWITH VOLTAGE 13 FN6047.8

14 Typical Performance urves T A = +25, Unless Otherwise Specified (ontinued) t ON (ns) = -5V V = () - 1V = 0V (V) FIGURE 13. IBIT TURN-ON TIME vs SUPPLY VOLTAGE t OFF (ns) = -5V = 0V V = () - 1V (V) FIGURE 14. IBIT TURN-OFF TIME vs SUPPLY VOLTAGE 300 V = () - 1V 250 V = () - 1V 250 = 0V 200 t RANS (ns) (V) FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE t RANS (ns) V± (V) +85 FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE NORMALIZED GAIN (db) V S = ±5V GAIN PHASE V IN = 0.2V P-P TO 5V P-P ISL84053 ISL84051 ISL84053 ISL PHASE ( ) 180 = 50Ω 1M 10M M 600M FREQUENY (Hz) FIGURE 17. FREQUENY RESPONSE FIGURE 18. ROSSTALK AND OFF ISOLATION 14 FN6047.8

15 Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: ISL84051: 193 ISL84052: 193 ISL84053: 193 PROESS: Si Gate MOS 15 FN6047.8

16 Small Outline Plastic Packages (SOI) N INDEX AREA e D B 0.25(0.010) M A M E -B- -A- -- SEATING PLANE A B S H 0.25(0.010) M B A1 0.10(0.004) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. α L M h x 45 M16.15 (JEDE MS-012-A ISSUE ) 16 LEAD NARROW BODY SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B D E e BS 1.27 BS - H h L N α Rev. 1 6/05 16 FN6047.8

17 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA (0.002) e D 0.10(0.004) M A M E1 -B- -Ab -- SEATING PLANE A B S E 0.25(0.010) M B A1 NOTES: 1. These package dimensions are within allowable dimensions of JEDE MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm ( inch). 10. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. (Angles in degrees) α GAUGE PLANE 0.10(0.004) A2 M L c M LEAD THIN SHRINK SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b c D E e BS 0.65 BS - E L N α 0 o 8 o 0 o 8 o - Rev. 1 2/02 17 FN6047.8

18 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) N INDEX AREA e D B 0.17(0.007) M A M E -B- -A- -- SEATING PLANE A B S H 0.25(0.010) M B A1 NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of B dimension at maximum material condition. 10. ontrolling dimension: INHES. onverted millimeter dimensions are not necessarily exact. α GAUGE PLANE 0.10(0.004) A2 M h x 45 L M16.15A 16 LEAD SHRINK SMALL OUTLINE PLASTI PAKAGE (0.150 WIDE BODY) INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B D E e BS BS - H h L N α Rev. 2 6/04 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil orporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see 18 FN6047.8