DATASHEET. Features. Applications ISL GHz, 4x1 Multiplexing Amplifier with Synchronous Controls. FN7451 Rev 3.00 Page 1 of 13.

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1 NOT REOMMENDED FOR NEW DESIGNS NO REOMMENDED REPLAEMENT contact our Technical Support enter at -888-INTERSIL or GHz, 4x Multiplexing Amplifier with Synchronous ontrols DATASHEET FN745 Rev 3. August 6, 22 The ISL59444 is a single-output 4: MUX-amp. The MUX-amp has a fixed gain of and a GHz bandwidth. The ISL59444 is ideal for professional video switching, HDTV, computer display routing, and other high performance applications. The device contains logic inputs for channel selection (S, S), latch control signals (LE, LE2), and a three-state output control (HIZ) for individual selection of MUX amps that share a common video output line. All logic inputs have pull-downs to ground and may be left floating. TABLE. TRUTH TABLE LE/LE2 HIZ S S OUT IN IN IN2 IN3 X X X HiZ Features GHz (-3dB) Bandwidth (V OUT = 2mV P-P ) 22MHz (-3dB) Bandwidth (V OUT = 2V P-P ) Slew Rate (R L = 5Ω V OUT = 4V) V/µs Slew Rate (R L = 5Ω V OUT = 5V) V/µs High Speed Three-State Output (HIZ) Pb-Free Plus Anneal Available (RoHS ompliant) Applications HDTV/DTV Analog Inputs Video Projectors omputer Monitors Set-top Boxes Security Video Broadcast Video Equipment RGB Video Distribution Systems RF Switching and Routing S S DEODE HIZ LE LE2 kω EN D L Q EN D L Q EN2 D L Q EN3 D L Q kω D L Q D L Q D L Q D L Q IN IN IN2 IN3 OUT LE LE2 S, S, HIZ OUT HX HY HZ HX HY HX HX HZ HZ FIGURE. FUNTIONAL DIAGRAM FIGURE 2. TIMING DIAGRAM FN745 Rev 3. Page of 3 August 6, 22

2 Pin onfiguration ISL59444 (6 LD SO) TOP VIEW IN NI IN GND IN2 NI IN S 4 S 3 HIZ 2 OUT LE2 LE NI 8 9 Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT IRUIT DESRIPTION IN ircuit Input for channel 2, 6, 8 NI Not Internally onnected; it is recommended this pin be tied to ground to minimize crosstalk. 3 IN ircuit Input for channel 4 GND ircuit 4 Ground pin 5 IN2 ircuit Input for channel 2 7 IN3 ircuit Input for channel 3 9 V - ircuit 4 Negative Power Supply LE ircuit 2 Synchronized channel switching: When LE is low, the master control latch loads the next switching address. The Mux Amp is configured for this address when LE2 goes low. Synchronized operation results when LE2 is the inverse of LE. hannel selection is asynchronous (changes with any control signal change) if both LE and LE2 are both low. LE2 ircuit 2 Synchronized channel switching: When LE2 is low, the newly selected channel, stored in the master latch via LE is selected. Synchronized operation results when LE2 is the inverse of LE. hannel selection is asynchronous (changes with any control signal change) if both LE and LE2 are both low. 2 OUT ircuit 3 Output 3 HIZ ircuit 2 Output disable (active high); there are internal pull-down resistors, so the device will be active with no connection; HI puts the output in high impedance state. 4 S ircuit 2 hannel selection pin MSB (binary logic code) FN745 Rev 3. Page 2 of 3 August 6, 22

3 Pin Descriptions (ontinued) PIN NUMBER PIN NAME EQUIVALENT IRUIT DESRIPTION 5 S ircuit 2 hannel selection pin LSB (binary logic code) 6 ircuit 4 Positive power supply IN LOGIPIN 2k +.2V - 33k GND. IRUIT IRUIT 2 OUT GND APAITIVELY OUPLED ESD LAMP IRUIT 3 IRUIT 4 Ordering Information PART NUMBER (Notes, 2, 3) PART MARKING TAPE & REEL PAKAGE (Note 4) PKG. DWG. # ISL59444IBZ 59444IBZ - 6 Ld SO (Pb-free) MDP27 ISL59444IBZ-T IBZ 7 6 Ld SO (Pb-free) MDP27 ISL59444IBZ-T IBZ 3 6 Ld SO (Pb-free) MDP27 NOTES:. Please refer to TB347 for details on reel specifications. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD For Moisture Sensitivity Level (MSL), please see device information page for ISL For more information on MSL please see tech brief TB SO6 (.5 ) FN745 Rev 3. Page 3 of 3 August 6, 22

4 Absolute Maximum Ratings (T A = +25 ) Supply Voltage ( to ) V Input Voltage V, +.5V Supply Turn-on Slew Rate V/µs Digital and Analog Input urrent (Note 5) mA Output urrent (ontinuous) mA ESD Rating Human Body Model (Per MIL-STD-883 Method 35.7) kV Machine Model V Thermal Information Storage Temperature Range to +5 Ambient Operating Temperature to +85 Operating Junction Temperature to +25 Power Dissipation See Figures 2 and 22 JA See Figures 2 and 22 AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 5. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T = T A Electrical Specifications = +5V, = -5V, GND = V, T A = +25, R L = 5Ω to GND, V HIZ =.8V, unless otherwise specified. PARAMETER DESRIPTION ONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT GENERAL I S Supply urrent (V OUT = V) No load, V HIZ =.8V ma No load, V HIZ = 2.V ma V OUT Positive and Negative Output Swing V IN = ±3.5V, R L = 5Ω ±3.2 ±3.44 V I OUT Output urrent R L = Ω to GND ±8 ±2 ±8 ma V OS Output Offset Voltage mv Ib Input Bias urrent V IN = V µa R out Output Resistance HIZ = logic high, (D), A V =.4 MW HIZ = logic low, (D), A V =.2 Ω R IN Input Resistance V IN = ±3.5V MΩ IN Input apacitance. pf A L or A V Voltage Gain V IN = ±.5V, R L = 5Ω V/V I TRI Output urrent in Three-state V OUT = V µa LOGI V H Input High Voltage (Logic Inputs) 2 V V L Input Low Voltage (Logic Inputs).8 V I IH Input High urrent (Logic Inputs) 5 5 µa I IL Input Low urrent (Logic Inputs) - 5 µa t LE LE, LE2 Minimum Pulse Width ns A GENERAL -3dB BW -3dB Bandwidth V OUT = 2mV P-P, L =.6pF. GHz V OUT = 2V P-P, L = 23.6pF, 23 MHz.dB BW.dB Bandwidth V OUT = 2mV P-P, L =.6pF 8 MHz V OUT = 2V P-P, L = 23.6pF, 5 MHz dg Differential Gain Error NTS-7, R L = 5. % FN745 Rev 3. Page 4 of 3 August 6, 22

5 Electrical Specifications = +5V, = -5V, GND = V, T A = +25, R L = 5Ω to GND, V HIZ =.8V, unless otherwise specified. (ontinued) PARAMETER DESRIPTION ONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT dp Differential Phase Error NTS-7, R L = 5.2 +SR Slew Rate 25% to 75%, V OUT = 5V, R L = 5Ω, L = 23.6pF, -SR Slew Rate 25% to 75%, V OUT = 5V, R L = 5Ω, L = 23.6pF, PSRR Power Supply Rejection Ratio D, PSRR and combined V± = ±4.5V to ±5.5V ISO hannel Isolation f = MHz, h-h X-Talk and Off Isolation, L =.6pF 55 V/µs 55 V/µs db 75 db SWITHING HARATERISTIS V GLITH hannel-to-hannel Switching Glitch V IN = V, L = 23.6pF, 38 mv P-P HIZ Switching Glitch V IN = V, L = 23.6pF, 75 mv P-P t SW-L-H hannel Switching Time Low to High.2V logic threshold to % movement of analog output t SW-H-L hannel Switching Time High to Low.2V logic threshold to % movement of analog output 32 ns 29 ns TRANSIENT RESPONSE tr, tf Rise and Fall Time, % to 9% V OUT = 2mV P-P, L =.6pF.68 ns V OUT = 2V P-P, L = 23.6pF, t S.% Settling Time V OUT = 2V P-P, L = 23.6pF,.4 ns 6.8 ns t PLH t PHL Propagation Delay - Low to High, % to % Propagation Delay- High to Low, % to % V OUT = 2mV P-P, L =.6pF.5 ns V OUT = 2V P-P, L = 23.6pF,.85 ns V OUT = 2mV P-P, L =.6pF.54 ns V OUT = 2V P-P, L = 23.6pF,.88 ns O S Overshoot V OUT = 2mV P-P, L =.6pF 8.3 % V OUT = 2V P-P, L = 23.6pF, 5.7 % NOTE: 6. Parameters with MIN and/or MAX limits are % tested at +25, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN745 Rev 3. Page 5 of 3 August 6, 22

6 Typical Performance urves V S = ±5V, R L = 5Ω to GND, T A = +25, unless otherwise specified. 5 4 V OUT = 2mV P-P 3 L = 9.7pF 2 L = 7.2pF - L = 5.5pF -2 L =.6pF -3-4 L INLUDES.6pF BOARD APAITANE FREQUENY (GHz) FIGURE 3. SMALL SIGNAL GAIN vs FREQUENY vs L V OUT = 2mV P-P L =.6pF R L = 5Ω FREQUENY (GHz) R L = kω R L = 75Ω R L = 5Ω FIGURE 4. SMALL SIGNAL GAIN vs FREQUENY vs R L V OUT = 2V P-P L = 6.6pF -2 L = 23.6pF -3-4 L INLUDES.6pF BOARD APAITANE L = 28.6pF FREQUENY (GHz) L =.6pF FIGURE 5. LARGE SIGNAL GAIN vs FREQUENY vs L V OUT = 2V P-P L = 23.6pF -3-4 R L = 5Ω R L = 75Ω R L = kω FREQUENY (GHz) R L = 5Ω FIGURE 6. LARGE SIGNAL GAIN vs FREQUENY vs R L.5.4 V OUT = 2mV P-P L = 9.7pF.3.2 L = 7.2pF L = 5.5pF L INLUDES.6pF L =.6pF BOARD APAITANE FREQUENY (GHz) FIGURE 7. SMALL SIGNAL.dB GAIN vs FREQUENY vs L V OUT = 2mV P-P L =.6pF R L = 5Ω -.4 R L = 75Ω FREQUENY (GHz) R L = kω R L = 5Ω FIGURE 8. SMALL SIGNAL.dB GAIN vs FREQUENY vs R L FN745 Rev 3. Page 6 of 3 August 6, 22

7 Typical Performance urves V S = ±5V, R L = 5Ω to GND, T A = +25, unless otherwise specified. (ontinued) L = 6.6pF V OUT = 2V P-P L = 23.6pF L INLUDES.6pF L = 28.6pF BOARD APAITANE FREQUENY (GHz) L =.6pF FIGURE 9. LARGE SIGNAL.dB GAIN vs FREQUENY vs L V OUT = 2V P-P L = 23.6pF R L = 5Ω R L = 75Ω R L = 5Ω FREQUENY (GHz) R L = kω FIGURE. LARGE SIGNAL.dB GAIN vs FREQUENY vs R L PSRR (db) V IN = 2mV P-P L = 23.6pF (db) V IN = V P-P L = 23.6pF ROSSTALK -5 PSRR () -6-7 PSRR () -8.3 FREQUENY (MHz) FIGURE. PSRR HANNELS -8-9 OFF ISOLATION FREQUENY (MHz) FIGURE 2. ROSSTALK AND OFF ISOLATION V OUT = mv P-P 6 R F = 5Ω OUTPUT RESISTANE (Ω) INPUT VOLTAGE NOISE (nv/ Hz) FREQUENY (MHz). FREQUENY (khz) FIGURE 3. R OUT vs FREQUENY FIGURE 4. INPUT NOISE vs FREQUENY FN745 Rev 3. Page 7 of 3 August 6, 22

8 Typical Performance urves V S = ±5V, R L = 5Ω to GND, T A = +25, unless otherwise specified. (ontinued) S, S S, S V/DIV V/DIV 2mV/DIV V OUT 5mV/DIV V OUT 2ns/DIV FIGURE 5. HANNEL TO HANNEL SWITHING GLITH V IN =V, R S = 25, L = 23.6pF 2ns/DIV FIGURE 6. HANNEL TO HANNEL TRANSIENT RESPONSE V IN =V, R S =25, L = 23.6pF HIZ HIZ V/DIV V/DIV mv/div V OUT 5mV/DIV V OUT 2ns/DIV FIGURE 7. HIZ SWITHING GLITH V IN = V, R S = 25, L = 23.6pF 2ns/DIV FIGURE 8. HIZ TRANSIENT RESPONSE V IN = V, R S = 25, L = 23.6pF 6 2 L =.6pF R L = 5Ω OUTPUT VOLTAGE (mv) TIME (4ns/DIV) OUTPUT VOLTAGE (V) L = 23.6pF R L = 5Ω TIME (4ns/DIV) FIGURE 9. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 2. LARGE SIGNAL TRANSIENT RESPONSE FN745 Rev 3. Page 8 of 3 August 6, 22

9 Typical Performance urves V S = ±5V, R L = 5Ω to GND, T A = +25, unless otherwise specified. (ontinued) POWER DISSIPATION (W) JEDE JESD5-7 HIGH EFFETIVE THERMAL ONDUTIVITY TEST BOARD.25W SO6 (.5 ) JA = 8 /W POWER DISSIPATION (W) JEDE JESD5-3 LOW EFFETIVE THERMAL ONDUTIVITY TEST BOARD..9 99mW.8 SO6 (.5 ) JA = /W AMBIENT TEMPERATURE ( ) AMBIENT TEMPERATURE ( ) FIGURE 2. PAKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 22. PAKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE A Test ircuits V IN 5Ω OR 75Ω ISL59444 L 2pF R L 5Ω V IN 5Ω OR 75Ω ISL59444 R S 475Ω L 2pF 5Ω OR 75Ω TEST EQUIPMENT 5Ω OR 75Ω FIGURE 23A. TEST IRUIT WITH OPTIMAL OUTPUT LOAD FIGURE 23B. TEST IRUIT FOR MEASURING WITH A 5Ω OR 75Ω INPUT TERMINATED EQUIPMENT V IN 5Ω OR 75Ω ISL59444 R S 5Ω OR 75Ω L 2pF TEST EQUIPMENT 5Ω OR 75Ω FIGURE 23. BAKLOADED TEST IRUIT FOR VIDEO ABLE APPLIATION. BANDWIDTH AND LINEARITY FOR R L LESS THAN 5Ω WILL BE DEGRADED. Figure 23A illustrates the optimum output load for testing A performance. Figure 23B illustrates the optimum output load when connecting to input terminated equipment. Figure 23 illustrates back loaded test circuit for video cable. FN745 Rev 3. Page 9 of 3 August 6, 22

10 Application ircuits * L = T + OUT V IN 5Ω - + T.6pF OUT pf V OUT R L = 5Ω * L : TOTAL LOAD APAITANE T : TRAE APAITANE OUT : OUTPUT APAITANE FIGURE 24A. SMALL SIGNAL 2mV P-P APPLIATION IRUIT V IN 5Ω - +.6pF T R S 25Ω OUT 22pF V OUT R L = 5Ω L = T + OUT FIGURE 24B. LARGE SIGNAL V P-P APPLIATION IRUIT FN745 Rev 3. Page of 3 August 6, 22

11 Application Information General The ISL59444 is a 4: mux that is ideal as a matrix element in high performance switchers and routers. The ISL59444 is optimized to drive a 2pF in parallel with a 5Ω load. The capacitance can be split between the PB capacitance an and external load capacitance. Their low input capacitance and high input resistance provide excellent 5Ω or 75Ω terminations. apacitance at the Output The output amplifier is optimized for capacitance to ground ( L ) directly on the output pin. Increased capacitance causes higher peaking with an increase in bandwidth. The optimum range for most applications is ~.pf to ~6pF. The optimum value can be achieved through a combination of P board trace capacitance ( T ) and an external capacitor ( OUT). A good method to maintain control over the output pin capacitance is to minimize the trace length ( T ) to the next component, and include a discrete surface mount capacitor ( OUT ) directly at the output pin. For large signal applications where overshoot is important the circuit in Figure 24B should be used. The series resistor (R S ) and capacitor ( L ) form a low pass network that limits system bandwidth and reduces overshoot. The component values shown result in a typical pulse response shown in Figure 2. Ground onnections For the best isolation and crosstalk rejection, the GND pin and NI pins must connect to the GND plane. The NI pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended this pin be tied to ground to minimize crosstalk. ontrol Signals S, S, HIZ - These pins are, TTL/MOS compatible control inputs. The S, S pins select which one of the inputs connect to the output. The HIZ pin is used to three-state the output amplifiers. For control signal rise and fall times less than ns the use of termination resistors close to the part will minimize transients coupled to the output. HIZ State An internal pull-down resistor connected to the HIZ pin ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 3ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance.4mω. Use this state to control the logic when more than one mux shares a common output. In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is basically the same as the active state. Latch State The latched control signals allow for synchronized channel switching. When LE is low the master control latch loads the next switching address (S, S), while the closed (assuming LE2 is the inverse of LE) slave control latch maintains the current state. LE2 switching low closes the master latch (with previous assumption), loads the now open slave latch, and switches the crosspoint to the newly selected channel. hannel selection is asynchronous (changes with any control signal change) if both LE and LE2 are low. Power-Up onsiderations The ESD protection circuits use internal diodes from all pins the and supplies. In addition, a dv/dt triggered clamp is connected between the and pins, as shown in the Equivalent ircuits through 4 section of the Pin Descriptions on page 2. The dv/dt triggered clamp imposes a maximum supply turn-on slew rate of V/µs. Damaging currents can flow for power supply rates-of-rise in excess of V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. onsideration must be given to the order in which power is applied to the and pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR55T or equivalent) connected from to ground and to ground (Figure 25) will shunt damaging currents away from the internal and ESD diodes in the event that the supply is applied to the device before the supply. If positive voltages are applied to the logic or analog video input pins before is applied, current will flow through the internal ESD diodes to the pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than. Limiting the Output urrent No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 5mA. Adequate thermal heat sinking of the parts is also required. FN745 Rev 3. Page of 3 August 6, 22

12 P Board Layout The frequency response of this circuit depends greatly on the care taken in designing the P board. The following are recommendations to achieve optimum high frequency performance from your P board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PB traces greater than " begin to exhibit transmission line characteristics with signal rise/fall times of ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip lines are used. Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. Maximize use of A de-coupled PB layers. All signal I/O lines should be routed over continuous ground planes (i.e., no split planes or PB gaps under these lines). Avoid vias in the signal I/O lines. Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. Minimum of 2 power supply de-coupling capacitors are recommended (pf,.µf) as close to the devices as possible. Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. The NI pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. SUPPLY LOGI POWER GND SIGNAL DE-OUPLING APS SUPPLY SHOTTKY PROTETION S GND IN IN LOGI ONTROL OUT EXTERNAL IRUITS FIGURE 25. SHOTTKY PROTETION IRUIT opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN745 Rev 3. Page 2 of 3 August 6, 22

13 Small Outline Package Family (SO) A D h X 45 N (N/2)+ E E PIN # I.D. MARK c A SEE DETAIL X B. M A B (N/2) L e H A2 SEATING PLANE GAUGE PLANE..4. M A B b A DETAIL X L 4 ±4 MDP27 SMALL OUTLINE PAKAGE FAMILY (SO) INHES SO6 SO6 (.3 ) SO2 SO24 SO28 SYMBOL SO-8 SO-4 (.5 ) (SOL-6) (SOL-2) (SOL-24) (SOL-28) TOLERANE NOTES A MAX - A A b c D , 3 E E , 3 e Basic - L L Basic - h Reference - N Reference - Rev. M 2/7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included. 2. Plastic interlead protrusions of. maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.5M-994 FN745 Rev 3. Page 3 of 3 August 6, 22