DATASHEET ISL84541, ISL84542, ISL84543, ISL Features. Applications. Related Literature

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1 DATASHEET ISL8441, ISL844, ISL844, ISL8444 Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches FN01 Rev 7.00 The Intersil ISL8441 ISL8444 devices are precision, dual analog switches designed to operate from a single +.7V to +1V supply. Targeted applications include battery powered equipment that benefit from the devices low power consumption ( W), low leakage currents (100pA max), and fast switching speeds (t ON = ns, t OFF = ns). ell phones, for example, often face ASI functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to mux-in additional functionality while reducing ASI design risk. Some of the smallest packages are available alleviating board space limitations, and making Intersil s newest line of low-voltage switches an ideal solution. The ISL8441/ISL844/ISL844 are dual singlepole/single-throw (SPST) devices. The ISL8441 has two normally open (NO) switches; the ISL844 has two normally closed (N) switches; the ISL844 has one NO and one N switch and can be used as an SPDT. The ISL8444 is a committed SPDT, which is perfect for use in -to-1 multiplexer applications. Table 1 summarizes the performance of this family. For higher performance, pin compatible versions, see the ISL410 - and ISL410 datasheet. NUMBER OF SWITHES Related Literature TABLE 1. FEATURES AT A GLANE ISL8441 ISL844 ISL844 ISL SW 1 / SW NO / NO N / N NO / N SPDT.V R ON V t ON / t OFF 0 / 0ns 0 / 0ns 0 / 0ns 0 / 0ns V R ON V t ON / t OFF / ns / ns / ns / ns PAKAGES 8 Ld PDIP, 8 Ld SOI, 8 Ld SOT-, 8 Ld MSOP 8 Ld PDIP, 8 Ld SOI, 8 Ld SOT- 8 Ld PDIP, 8 Ld SOI, Ld SOT- Technical Brief TB Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Features Pb-free Available as an Option Drop-in Replacements for MAX441 - MAX444, DG941, DG9 - DG9 Fully Specified at.v and V Supplies Pin ompatible with MAX - MAX ON Resistance (R ON ) R ON Matching Between hannels <1 Low harge Injection p (Max) Single Supply Operation V to +1V Low Power onsumption (P D ) < W Low Leakage urrent (Max at 8 o ) nA Fast Switching Action - t ON ns - t OFF ns Guaranteed Break-Before-Make (ISL844/ISL8444 only) Minimum 000V ESD Protection per Method 01.7 TTL, MOS ompatible Available in SOT- Packaging Applications Battery Powered, Handheld, and Portable Equipment - ellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops ommunications Systems - Military Radios - PBX, PABX Test Equipment - Ultrasound - Electrocardiograph Heads-Up Displays Audio and Video Switching Various ircuits - +V/+V DAs and ADs - Sample and Hold ircuits - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset ircuits FN01 Rev 7.00 Page 1 of 18

2 Pinouts (Note 1) ISL8441 (PDIP, SOI, MSOP) ISL8441 (SOT-) NO NO OM 1 OM 1 7 IN 1 7 IN 1 IN OM IN 4 NO OM 4 NO ISL844 (PDIP, SOI) ISL844 (SOT-) N N OM 1 OM 1 7 IN 1 7 IN 1 IN OM IN 4 N OM 4 N ISL844 (PDIP, SOI) ISL844 (SOT-) NO NO OM 1 OM 1 7 IN 1 7 IN 1 IN OM IN 4 N OM 4 N ISL8444 (PDIP, SOI) ISL8444 (SOT-) NO 1 8 IN 1 NO OM 7 IN OM N 4 N N 4 N NOTE: 1. Switches Shown for Logic 0 Input. Truth Table ISL8441 ISL844 ISL844 ISL8444 Pin Descriptions PIN FUNTION LOGI SW 1, SW 1, SW 1 SW PIN N PIN NO System Power Supply Input (+.7V to +1V) 0 OFF ON OFF ON ON OFF 1 ON OFF ON OFF OFF ON IN Ground onnection Digital ontrol Input NOTE: Logic 0 0.8V. Logic 1.4V. OM Analog Switch ommon Pin NO Analog Switch Normally Open Pin N Analog Switch Normally losed Pin N.. No Internal onnection FN01 Rev 7.00 Page of 18

3 Ordering Information PART NO. (BRAND) ISL8441PZ ISL8441BZ-T) ISL8441BZ (Note ) ISL8441BZ-T (Note ) ISL8441IPZ ISL8441BZ-T) ISL8441IBZ (Note ) ISL8441IBZ-T (Note ) ISL8441IUZ (41I) ISL8441BZ-T) ISL8441IUZ-T (41I) ISL8441BZ-T) ISL844PZ ISL8441BZ-T) ISL844BZ ISL8441BZ-T) ISL844BZ-T ISL8441BZ-T) ISL844IPZ ISL8441BZ-T) TEMP. RANGE ( o ) PAKAGE (RoHS ompliant) 0 to 70 8 Ld PDIP E8. PKG. DWG. # 0 to 70 8 Ld SOI M8.1 8 Ld SOI Tape and Reel M to 8 8 Ld PDIP E to 8 8 Ld SOI M8.1 8 Ld SOI Tape and Reel M to 8 8 Ld MSOP M Ld MSOP Tape and Reel M to 70 8 Ld PDIP E8. 0 to 70 8 Ld SOI M8.1 8 Ld SOI Tape and Reel M to 8 8 Ld PDIP E8. Ordering Information PART NO. (BRAND) ISL844IBZ ISL8441BZ-T) ISL844IBZ-T ISL8441BZ-T) ISL844IHZ-T (4I) ISL8441BZ-T) ISL844PZ ISL8444BZ-T) ISL844BZ ISL8444BZ-T) ISL844BZ-T ISL8444BZ-T) ISL844IPZ ISL8444BZ-T) ISL844IBZ ISL8444BZ-T) ISL844IBZ-T ISL8444BZ-T) TEMP. RANGE ( o ) PAKAGE (RoHS ompliant) -40 to 8 8 Ld SOI M8.1 8 Ld SOI Tape and Reel M8.1 8 Ld SOT- Tape and Reel P to 70 8 Ld PDIP E8. 0 to 70 8 Ld SOI M8.1 8 Ld SOI Tape and Reel M to 8 8 Ld PDIP E to 8 8 Ld SOI M8.1 8 Ld SOI Tape and Reel M8.1 PKG. DWG. # FN01 Rev 7.00 Page of 18

4 Ordering Information PART NO. (BRAND) ISL844IHZ-T (4I) ISL8444BZ-T) ISL8444PZ ISL8444BZ-T) ISL8444BZ (Note ) ISL8444BZ-T (Note ) ISL8444IPZ ISL8444BZ-T) ISL8444IBZ (Note ) ISL8444IBZ-T (Note ) ISL8444IHZ-T (44I) (Note ) TEMP. RANGE ( o ) PAKAGE (RoHS ompliant) 8 Ld SOT- Tape and Reel P to 70 8 Ld PDIP E8. 0 to 70 8 Ld SOI M8.1 8 Ld SOI Tape and Reel M to 8 8 Ld PDIP E8. PKG. DWG. # -40 to 8 8 Ld SOI M8.1 8 Ld SOI Tape and Reel M8.1 Ld SOT- Tape and Reel P.04 NOTE:. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J Std-00B. FN01 Rev 7.00 Page 4 of 18

5 Absolute Maximum Ratings to to1v Input Voltages IN (Note ) to (() + 0.V) NO, N (Note ) to (() + 0.V) Output Voltages OM (Note ) to (() + 0.V) ontinuous urrent (Any Terminal) mA Peak urrent, IN, NO, N, or OM (Pulsed 1ms, 10% Duty ycle, Max) mA ESD Rating (Per MIL-STD-88 Method 01) >kV Operating onditions Temperature Range ISL844XX o to 70 o ISL844XIX o to 8 o Thermal Information Thermal Resistance (Typical, Note 4) JA ( o /W) Ld SOT- Package Ld SOT- Package Ld MSOP Package LD SOI Package LD PDIP Package Maximum Junction Temperature (Plastic Package) o Moisture Sensitivity (See Technical Brief TB) All Other Packages Level 1 8 Ld SOT- Package Level Maximum Storage Temperature Range o to 10 o Maximum Lead Temperature (Soldering 10s) o (SOI, MSOP and SOT- - Lead Tips Only) AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Signals on N, NO, OM, or IN exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 4. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB79 for details. Electrical Specifications - V Supply Test onditions: = +4.V to +.V, = 0V, V INH =.4V, V INL = 0.8V (Note ), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( o ) MIN (NOTE ) TYP MAX (NOTE ) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0 - V ON Resistance, R ON = 4.V, I OM = 1.0mA, V NO or V N =.V, See Figure Full R ON Matching Between hannels, = V, I OM = 1.0mA, V NO or V N =.V R ON Full R ON Flatness, R FLAT(ON) = V, I OM = 1.0mA, V NO or V N = 1V, V, V Full NO or N OFF Leakage urrent, =.V, V OM = 1V, 4.V, V NO or V N = 4.V, 1V, I NO(OFF) or I N(OFF) Note na Full - - na OM OFF Leakage urrent, I OM(OFF) =.V, V OM = 4.V, 1V, V NO or V N = 1V, 4.V, Note na Full - - na OM ON Leakage urrent, I OM(ON) V =.V, V OM = 1V, 4.V, or V NO or V N = 1V, 4.V, or Floating, Note na Full na FN01 Rev 7.00 Page of 18

6 Electrical Specifications - V Supply Test onditions: = +4.V to +.V, = 0V, V INH =.4V, V INL = 0.8V (Note ), Unless Otherwise Specified (ontinued) PARAMETER TEST ONDITIONS TEMP ( o ) MIN (NOTE ) TYP MAX (NOTE ) UNITS DYNAMI HARATERISTIS Turn-ON Time, t ON V NO or V N = V, R L =1k, L = pf, V IN = 0 to V, See Figure ns Full ns Turn-OFF Time, t OFF V NO or V N = V, R L =1k, L = pf, V IN = 0 to V, See Figure 1-7 ns Full ns Break-Before-Make Time Delay (ISL844, ISL8444), t D R L = 00, L = pf, V NO = V N = V, V IN = 0 to V, See Figure Full 10 - ns harge Injection, Q L = 1.0nF, V G = 0V, R G = 0, See Figure - 1 p OFF Isolation R L = 0, L = pf, f = 1MHz, See Figure db rosstalk (hannel-to-hannel) R L = 0, L = pf, f = 1MHz, See Figure db NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = 0V, See Figure pf OM OFF apacitance, f = 1MHz, V NO or V N = V OM = 0V, See Figure pf OM(OFF) OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = 0V, See Figure 7, ISL8441// pf f = 1MHz, V NO or V N = V OM = 0V, See Figure 7, ISL pf POWER SUPPLY HARATERISTIS Power Supply Range Full.7 1 V Positive Supply urrent, I+ =.V, V IN = 0V or, all channels on or off Full A DIGITAL HARATERISTIS Input Voltage Low, V INL Full V Input Voltage High, V INH Full V NOTES:. V IN = input voltage to perform proper function.. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at o. FN01 Rev 7.00 Page of 18

7 Electrical Specifications -.V Supply Test onditions: = +.0V to +.V, = 0V, V INH =.4V, V INL = 0.8V (Note ), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( o ) MIN (NOTE ) TYP MAX (NOTE ) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0 - V ON Resistance, R ON = V, I OM = 1.0mA, V NO or V N = 1.V Full R ON Matching Between hannels, =.V, I OM = 1.0mA, V NO or V N = 1.V R ON Full R ON Flatness, R FLAT(ON) =.V, I OM = 1.0mA, V NO or V N = 0.V, 1V, 1.V - 10 Full NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) =.V, V OM = 1V, V, V NO or V N = V, 1V, Note 7 OM OFF Leakage urrent, I OM(OFF) =.V, V OM = V, 1V, V NO or V N = 1V, V, Note 7 OM ON Leakage urrent, I OM(ON) V =.V, V OM = 1V, V, or V NO or V N = 1V, V, or floating, Note na Full - - na na Full - - na na Full na DYNAMI HARATERISTIS Turn-ON Time, t ON V NO or V N = 1.V, R L =1k, L = pf, V IN = 0 to V ns Full 00 ns Turn-OFF Time, t OFF V NO or V N = 1.V, R L =1k, L = pf, V IN = 0 to V ns Full ns Break-Before-Make Time Delay (ISL844, ISL8444), t D R L = 00, L = pf, V NO or V N = 1.V, V IN = 0 to V Full 0 - ns harge Injection, Q L = 1.0nF, V G = 0V, R G = 0-1 p OFF Isolation R L = 0, L = pf, f = 1MHz db rosstalk (hannel-to-hannel) db NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = 0V pf OM OFF apacitance, f = 1MHz, V NO or V N = V OM = 0V pf OM(OFF) OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = 0V, ISL8441// pf POWER SUPPLY HARATERISTIS f = 1MHz, V NO or V N = V OM = 0V, ISL pf Positive Supply urrent, I+ =.V, V IN = 0V or, all channels on or off Full -1-1 A DIGITAL HARATERISTIS Input Voltage Low, V INL Full V Input Voltage High, V INH Full V Input urrent, I INH, I INL =.V, V IN = 0V or Full -1-1 A FN01 Rev 7.00 Page 7 of 18

8 Test ircuits and Waveforms LOGI V 0V 0% t r < 0ns t f < 0ns SWITH SWITH OUTPUT V NO 0V t OFF 90% V OUT 90% SWITH LOGI NO or N IN OM R L 1k V OUT L pf t ON Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITHING TIMES Repeat test for all switches. L includes fixture and stray capacitance. R L V OUT = V (NO or N) R L + R ON FIGURE 1B. TEST IRUIT SWITH OUTPUT V OUT V OUT R G NO or N OM V OUT LOGI ON OFF ON 0V V G IN L Q = V OUT x L LOGI FIGURE A. MEASUREMENT POINTS FIGURE. HARGE INJETION FIGURE B. TEST IRUIT LOGI V 0V V NX NO1 V OUT1 SWITH OUTPUT V OUT1 0V 90% N IN 1 OM 1 V OUT R L1 L1 OM 00 pf SWITH OUTPUT V OUT 0V t D t D 90% LOGI IN R L 00 L pf L includes fixture and stray capacitance. FIGURE A. MEASUREMENT POINTS (ISL844 ONLY) FIGURE B. TEST IRUIT (ISL844 ONLY) FN01 Rev 7.00 Page 8 of 18

9 Test ircuits and Waveforms (ontinued) LOGI SWITH OUTPUT V OUT V 0V 0V t D 90% V NX LOGI NO N IN OM R L 00 V OUT L pf L includes fixture and stray capacitance. FIGURE. MEASUREMENT POINTS (ISL8444 ONLY) FIGURE D. TEST IRUIT (ISL8444 ONLY) FIGURE. BREAK-BEFORE-MAKE TIME SIGNAL GENERATOR NO or N R ON = V 1 /1mA NO or N V NX IN X 0V or.4v 1mA V 1 IN 0.8V or.4v ANALYZER OM OM R L FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE. R ON TEST IRUIT SIGNAL GENERATOR NO1 or N1 OM1 0 NO or N 0V or.4v IN 1 IN 0V or.4v IMPEDANE ANALYZER IN X 0V or.4v ANALYZER R L OM NO or N N OM FIGURE. ROSSTALK TEST IRUIT FIGURE 7. APAITANE TEST IRUIT FN01 Rev 7.00 Page 9 of 18

10 Detailed Description The ISL8441 ISL8444 dual analog switches offer precise switching capability from a single.7v to 1V supply with low on-resistance (0 ) and high speed operation (t ON = ns, t OFF = ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (.7V), low power consumption ( W), low leakage currents (100pA max), and the tiny SOT- packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (see Figure 8). To prevent forward biasing these diodes, must be applied before any input signals, and input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low R ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR IN X V NO or N OPTIONAL PROTETION DIODE V OM OPTIONAL PROTETION DIODE FIGURE 8. OVERVOLTAGE PROTETION Power-Supply onsiderations The ISL844X construction is typical of most MOS analog switches, except that they have only two supply pins: and. and drive the internal MOS switches and set their analog voltage limits. Unlike switches with a 1V maximum supply voltage, the ISL844X 1V maximum supply voltage provides plenty of room for the 10% tolerance of 1V supplies, as well as room for overshoot and noise spikes. The minimum supply voltage is.7v. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. and also power the internal logic and level shifters. The level shifters convert the logic levels to switched and signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch family is TTL compatible (0.8V and.4v) over a supply range of V to 11V (see Figure 1). At 1V the V IH level is about.v. This is still below the TTL guaranteed high output minimum level of.8v, but noise margin is reduced. For best results with a 1V supply, use a logic family the provides a V OH greater than V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. High-Frequency Performance In systems, signal response is reasonably flat even past 00MHz (see Figure 1). Figure 1 also illustrates that the frequency response is very consistent over a wide range, and for varying analog signal levels. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch s input to its output. Off Isolation is the resistance to this feedthrough, while rosstalk indicates the amount of feedthrough from one switch to another. Figure 17 details the high Off Isolation and rosstalk rejection provided by this family. At 10MHz, off isolation is about 0dB in systems, decreasing approximately 0dB per decade as frequency increases. Higher load impedances decrease Off Isolation and rosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will FN01 Rev 7.00 Page 10 of 18

11 vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog-signal paths and or. Typical Performance urves T A = o, Unless Otherwise Specified R ON ( ) o 0 1 o -40 o (V) R ON ( ) o o 8 o o -40 o 8 o o -40 o =.V = V = 1V o V OM (V) FIGURE 9. ON RESISTANE vs SUPPLY VOLTAGE FIGURE 10. ON RESISTANE vs SWITH VOLTAGE R ON ( ) o 8 o -40 o 0. = V o o o o = 1V o 8 o -40 o o V OM (V) FIGURE 11. R ON MATH vs SWITH VOLTAGE =.V Q (p) = V = 1V 10 =.V V OM (V) FIGURE 1. HARGE INJETION vs SWITH VOLTAGE FN01 Rev 7.00 Page 11 of 18

12 Typical Performance urves T A = o, Unless Otherwise Specified (ontinued) t ON (ns) o o 0 o (V) FIGURE 1. TURN - ON TIME vs SUPPLY VOLTAGE t OFF (ns) 0 8 o -40 o -40 o 0 o (V) FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE V INH AND V INL (V).0. V INH o 8 o o 8 1. o -40 o 1.0 o V INL 8 o (V) FIGURE 1. DIGITAL SWITHING POINT vs SUPPLY VOLTAGE NORMALIZED GAIN (db) =.V to 1V GAIN PHASE R L = 0 V IN = 0.V P-P to.v P-P ( =.V) V IN = 0.V P-P to 4V P-P ( = V) V IN = 0.V P-P to V P-P ( = 1V) FREQUENY (MHz) FIGURE 1. FREQUENY RESPONSE PHASE (DEGREES) -10 = V to 1V Die haracteristics ROSSTALK (db) ISOLATION ROSSTALK OFF ISOLATION (db) SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: ISL8441: ISL844: ISL844: ISL8444: 8 PROESS: Si Gate MOS k 10k 100k 1M 10M 100M 00M FREQUENY (Hz) FIGURE 17. ROSSTALK AND OFF ISOLATION FN01 Rev 7.00 Page 1 of 18

13 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION HANGE FN Ordering Information Table on page. - Added Revision History. - Added About Intersil Verbiage. *Updated POD M8.118 to most recent revision, changes are as follows: -Revision to Revision hanges: Updated to new intersil format by adding land pattern and moving dimensions from table onto drawing -Revision to Revision 4 hanges: orrected lead width dimension in side view 1 from " " to " " *Updated POD M8.1 to most current revision with changes as follows: -Revision 0 to Revision 1 hanges: POD created from MOL M8.1 -Revision 1 to Revision hanges: Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern -Revision to Revision hanges: hanged Note 1 "198" to "1994" hanged in Typical Recommended Land Pattern the following:.41(0.09) to.0(0.087) 0.7 (0.00) to 0.0(0.0) 0.00 to.0(0.0) -Revision to Revision 4 hanges: hanged Note 1 "198" to "1994" *Updated POD P.04 to most current revision with changes as follows: Updated to new format (same dimensions, added land pattern and moved dimensions from table onto drawing) About Intersil Intersil orporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN01 Rev 7.00 Page 1 of 18

14 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D1 B1 -- -A- N 1 N/ B D e D1 E1 -B- A (0.) M A A L B S NOTES: 1. ontrolling Dimensions: INH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y14.M Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A1 and L are measured with the package seated in JEDE seating plane gauge GS-.. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum e B and e are measured at the lead tips with the leads unconstrained. e must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.mm). 9. N is the maximum number of terminal positions. 10. orner leads (1, N, N/ and N/ + 1) for E8., E1., E18., E8., E4. will have a B1 dimension of inch ( mm). A e E L e A e B E8. (JEDE MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , D D E E e BS.4 BS - e A 0.00 BS 7. BS e B L N Rev. 0 1/9 FN01 Rev 7.00 Page 14 of 18

15 Package Outline Drawing M LEAD MINI SMALL OUTLINE PLASTI PAKAGE Rev 4, 7/11.0±0.0 8 A D DETAIL "X" 1.10 MAX SIDE VIEW ± ±0.1 PIN# 1 ID 0.9 REF 1 B 0. BS GAUGE PLANE 0. H 0.8± ± 0.1 DETAIL "X" ± SEATING PLANE M A-B D 0.10 ± SIDE VIEW 1 (.80) (4.40) (.00) NOTES: 1. Dimensions are in millimeters. (0.) (0.40).. 4. Dimensioning and tolerancing conform to JEDE MO-187-AA and AMSEY14.m Plastic or metal protrusions of 0.1mm max per side are not included. Plastic interlead protrusions of 0.1mm max per side are not included. (1.40). Dimensions are measured at Datum Plane "H". TYPIAL REOMMENDED LAND PATTERN. Dimensions in ( ) are for reference only. FN01 Rev 7.00 Page 1 of 18

16 Package Outline Drawing M8.1 8 LEAD NARROW BODY SMALL OUTLINE PLASTI PAKAGE Rev 4, 1/1 DETAIL "A" 1.7 (0.00) 0.40 (0.01) INDEX AREA 4.00 (0.17).80 (0.10).0 (0.44).80 (0.8) 0.0 (0.0) 0. (0.01) x SIDE VIEW B 0. (0.010) 0.19 (0.008).0 (0.087) SEATING PLANE (0.197) 4.80 (0.189) 1.7 (0.09) 1. (0.0) (0.0) 1.7 (0.00) (0.00) 0.1(0.00) 0.(0.01) 0.(0.010) 0.10(0.004) 4.0(0.0) SIDE VIEW A TYPIAL REOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.M Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.1mm (0.00 inch) per side.. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. Terminal numbers are shown for reference only.. The lead width as measured 0.mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.1mm (0.04 inch). 7. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. 8. This outline conforms to JEDE publication MS-01-AA ISSUE. FN01 Rev 7.00 Page 1 of 18

17 Package Outline Drawing P.04 LEAD SMALL OUTLINE TRANSISTOR PLASTI PAKAGE Rev 4, / A 0.9 D /-0.10 PIN 1 INDEX AREA x (0.0) B 0.40 ± M A-B D SEE DETAIL X END VIEW.90 ± TYP ( PLS) / MAX (0.) GAUGE PLANE 0.10 SEATING PLANE SIDE VIEW DETAIL "X" 0.4±0.1 4 (0.9) (0.0) (1.0) NOTES: (.40) Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.M Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. Package conforms to JEDE MO-178AB. TYPIAL REOMMENDED LAND PATTERN FN01 Rev 7.00 Page 17 of 18

18 Small Outline Transistor Plastic Packages (SOT-8) A L A b (0.008) M L e1 D L e 1 4 SEATING PLANE 4X 1 4X 1 WITH PLATING c A1 E 0.10 (0.004) BASE METAL L L1 VIEW b b1 R1 R L SEATING PLANE -- c1 VIEW GAUGE PLANE L E1 P LEAD SMALL OUTLINE TRANSISTOR PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b b c c D E E e 0.0 Ref 0. Ref - e Ref 1.9 Ref - L L Ref. 0.0 Ref. L Ref. 0. Ref. N 8 8 R R o 8 o 0 o 8 o - Rev. 9/0 NOTES: 1. Dimensioning and tolerance per ASME Y14.M Package conforms to EIAJ S-74 and JEDE MO178BA.. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane.. N is the number of terminal positions.. These Dimensions apply to the flat section of the lead between 0.08mm and 0.1mm from the lead tip. 7. ontrolling dimension: MILLIMETER. onverted inch dimensions are for reference only opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN01 Rev 7.00 Page 18 of 18