DATASHEET ISL Features. Applications. Related Literature

Transcription

1 DATASHEET ISL836 Ultra Low ON-Resistance, Low Voltage, Single Supply, Quad SPDT (Dual DPDT) Analog Switch FN64 Rev 3. The Intersil ISL836 device is a low ON-resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1.65V to +3.6V supply. Targeted applications include battery powered equipment that benefit from low on-resistance (.26 ), and fast switching speeds (t ON = ns, t OFF = 7ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. ell phones, for example, often face ASI functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to mux-in additional functionality while reducing ASI design risk. The ISL836 is offered in small form factor packages, alleviating board space limitations. The ISL836 consists of four SPDT switches. It is configured as a dual double-pole/double-throw (DPDT) device with two logic control inputs that control two SPDT switches each. The configuration can be used as a dual differential 2-to-1 multiplexer/demultiplexer. The ISL836 is pin compatible with the STG36. Related Literature TABLE 1. FEATURES AT A GLANE ISL836 Number of Switches 4 SW Quad SPDT (Dual DPDT) 3.V R ON.26 3.V t ON /t OFF ns/7ns 1.8V R ON V t ON /t OFF 18ns/ns Packages 16 Ld 3x3 QFN, 16 Ld TSSOP Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches Features Pb-Free Available as an Option (RoHS ompliant) (see Ordering Info) Drop in Replacement for the STG36 ON Resistance (R ON ) - = +3.V = +1.8V R ON Matching between hannels R ON Flatness Across Signal Range Single Supply Operation V to +3.6V Low Power onsumption (PD) <.2µW Fast Switching Action - t ON ns - t OFF ns Guaranteed Break-Before-Make 1.8V Logic ompatible (+3V supply) Available in 16 lead 3x3 QFN and 16 lead TSSOP ESD HBM Rating - Pins kv - All Other Pins kV Applications Battery Powered, Handheld, and Portable Equipment - ellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops Portable Test and Measurement Medical Equipment Audio and Video Switching FN64 Rev 3. Page 1 of 11

2 Pinouts (Note 1) Ordering Information ISL836 (TSSOP) TOP VIEW PART NO. (BRAND) TEMP. RANGE ( ) PAKAGE PKG. DWG. # NO ISL836IR (836IR) -4 to Ld 3x3 QFN L16.3x3 1 N N4 4 ISL836IR-T (836IR) -4 to Ld 3x3 QFN Tape and Reel L16.3x3 1-2 NO2 2 N NO4 3-4 N3 3 NO3 ISL836IV (836IV) ISL836IV-T (836IV) ISL836IRZ (836IR) (See Note) -4 to Ld TSSOP M to Ld TSSOP Tape and Reel -4 to Ld 3x3 QFN (Pb-free) M L16.3x3 ISL836 (3x3 QFN) TOP VIEW ISL836IRZ-T (836IR) (See Note) -4 to Ld 3x3 QFN Tape and Reel (Pb-free) L16.3x3 1 NO1 N ISL836IVZ (836IV) (See Note) -4 to Ld TSSOP (Pb-free) M N NO4 ISL836IVZ-T (836IV) (See Note) -4 to Ld TSSOP Tape and Reel (Pb-free) M NO N2 NO N3 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-2. NOTE: 1. Switches Shown for Logic Input. Truth Table LOGI N SW NO SW ON OFF 1 OFF ON NOTE: Logic.5V. Logic 1 1.4V with a 3V supply. Pin Descriptions P FUNTION System Power Supply Input (+1.65V to +3.6V) NO N Ground onnection Digital ontrol Input Analog Switch ommon Pin Analog Switch Normally Open Pin Analog Switch Normally losed Pin FN64 Rev 3. Page 2 of 11

3 Absolute Maximum Ratings to to 4.7V Input Voltages NO, N, (Note 2) to (() +.3V) Output Voltages (Note 2) to (() +.3V) ontinuous urrent NO, N, or mA Peak urrent NO, N, or (Pulsed 1ms, % Duty ycle, Max) mA ESD Rating: HBM X >kV HBM NO X, N X, X,, >4kV MM X >5V MM NO X, N X, X,, >3V DM >V Thermal Information Thermal Resistance (Typical, Note 3) JA ( /W) 16 Ld 3x3 QFN Package Ld TSSOP Package Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to 15 Maximum Lead Temperature (Soldering s) (Lead Tips Only) Operating onditions Temperature Range ISL836IX to 85 AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on N, NO,, or exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB37 for details. Electrical Specifications - 3V Supply Test onditions: = +2.7V to +3.3V, = V, V H = 1.4V, V L =.5V (Notes 4, 6), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) M TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON R ON Matching Between hannels, R ON R ON Flatness, R FLAT(ON) = 2.7V, I = ma, V NO or V N = V to, (See Figure 5) = 2.7V, I = ma, V NO or V N = Voltage at max R ON, (Note ) = 2.7V, I = ma, V NO or V N = V to, (Note 7) Full Full Full NO or N OFF Leakage urrent, = 3.3V, V =.3V, 3V, V NO or V N = 3V,.3V na I NO(OFF) or I N(OFF) Full -2-2 na ON Leakage urrent, I (ON) DYNAMI HARATERISTIS Turn-ON Time, t ON Turn-OFF Time, t OFF Break-Before-Make Time Delay, t D V = 3.3V, V =.3V, 3V, or V NO or V N =.3V, 3V, or Floating = 2.7V, V NO or V N = 1.5V, R L = 5, L = 35pF, (See Figure 1, Note 8) = 2.7V, V NO or V N = 1.5V, R L = 5, L = 35pF, (See Figure 1, Note 8) = 3.3V, V NO or V N = 1.5V, R L = 5, L = 35pF, (See Figure 3, Note 8) na Full na ns Full ns ns Full ns Full ns harge Injection, Q L = 1.nF, V G = V, R G =, (See Figure 2) p OFF Isolation R L = 5, L = 5pF, f = khz, V = 1V RMS, (See Figure 4) rosstalk (hannel-to-hannel) R L = 5, L = 5pF, f = khz, V = 1V RMS, (See Figure 6) db db Total Harmonic Distortion f = 2Hz to 2kHz, V = 2V P-P, R L = % FN64 Rev 3. Page 3 of 11

4 Electrical Specifications - 3V Supply Test onditions: = +2.7V to +3.3V, = V, V H = 1.4V, V L =.5V (Notes 4, 6), Unless Otherwise Specified (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) M TYP MAX UNITS NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V = V, (See Figure 7) pf ON apacitance, (ON) f = 1MHz, V NO or V N = V = V, (See Figure 7) pf POWER SUPPLY HARATERISTIS Power Supply Range Full V Positive Supply urrent, I+ = 3.6V, V = V or na DIGITAL HARATERISTIS Full na Input Voltage Low, V L Full V Input Voltage High, V H Full V Input urrent, I H, I L = 3.6V, V = V or (Note 8) Full A NOTES: 4. V = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are % tested at +25. Limits across the full temperature range are guaranteed by design and correlation. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Guaranteed but not tested.. R ON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value, between N1 and N2, N3 and N4 or between NO1 and NO2, NO3 and NO4. Electrical Specifications - 1.8V Supply Test onditions: = +1.65V to +2V, = V, V H = 1.V, V L =.4V (Notes 4, 6), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) M TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON DYNAMI HARATERISTIS Turn-ON Time, t ON Turn-OFF Time, t OFF Break-Before-Make Time Delay, t D = 1.8V, I = ma, V NO or V N = V to, (See Figure 5) = 1.65V, V NO or V N = 1.V, R L = 5, L = 35pF, (See Figure 1, Note 8) = 1.65V, V NO or V N = 1.V, R L = 5, L = 35pF, (See Figure 1, Note 8) = 2.V, V NO or V N = 1.V, R L = 5, L = 35pF, (See Figure 3, Note 8) Full ns Full ns ns Full ns Full ns harge Injection, Q L = 1.nF, V G = V, R G =, (See Figure 2) p OFF Isolation R L = 5, L = 5pF, f = khz, V = 1V RMS, (See Figure 4) rosstalk (hannel-to-hannel) R L = 5, L = 5pF, f = khz, V = 1V RMS, (See Figure 6) db db NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V = V, (See Figure 7) pf ON apacitance, (ON) f = 1MHz, V NO or V N = V = V, (See Figure 7) pf FN64 Rev 3. Page 4 of 11

5 Electrical Specifications - 1.8V Supply Test onditions: = +1.65V to +2V, = V, V H = 1.V, V L =.4V (Notes 4, 6), Unless Otherwise Specified (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) M TYP MAX UNITS DIGITAL HARATERISTIS Input Voltage Low, V L Full V Input Voltage High, V H Full V Input urrent, I H, I L = 2.V, V = V or (Note 8) Full A Test ircuits and Waveforms LOGI SWITH SWITH OUTPUT V V NO V 5% t ON t OFF % t r < 5ns t f < 5ns % Logic input waveform is inverted for switches that have the opposite logic sense. SWITH LOGI NO or N Repeat test for all switches. L includes fixture and stray capacitance. R L = V (NO or N) R L + R ON R L 5 L 35pF FIGURE 1A. MEASUREMENT POTS FIGURE 1. SWITHG TIMES FIGURE 1B. TEST IRUIT SWITH OUTPUT R G NO or N LOGI ON Q = x L OFF ON V V G LOGI L FIGURE 2A. MEASUREMENT POTS FIGURE 2. HARGE JETION FIGURE 2B. TEST IRUIT FN64 Rev 3. Page 5 of 11

6 Test ircuits and Waveforms (ontinued) LOGI V V NX NO N R L 5 L 35pF SWITH OUTPUT V t D % LOGI L includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST IRUIT SIGNAL GENERATOR NO or N R ON = V 1 /1mA NO or N V NX V or 1mA V 1 V or ANALYZER R L FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE 5. R ON TEST IRUIT SIGNAL GENERATOR NO or N 5 NO or N V or 1 IMPEDANE ANALYZER V or ANALYZER R L N or NO N.. FIGURE 6. ROSSTALK TEST IRUIT FIGURE 7. APAITANE TEST IRUIT FN64 Rev 3. Page 6 of 11

7 Detailed Description The ISL836 is a bidirectional, dual double-pole/ double-throw (DPDT) analog switch that offers precise switching capability from a single 1.65V to 3.6V supply with low on-resistance (.26 ) and high speed operation (t ON = ns, t OFF = 7ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65V), low power consumption (2.7 W max), low leakage currents (45nA max), and the tiny QFN and TSSOP packages. The ultra low on-resistance and Ron flatness provide very low insertion loss and distortion to applications that require signal reproduction. Supply Sequencing and Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (See Figure 8). To prevent forward biasing these diodes, must be applied before any input signals, and the input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (See Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low R ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (See Figure 8). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR X V NO or N OPTIONAL PROTETION DIODE V OPTIONAL PROTETION DIODE FIGURE 8. OVERVOLTAGE PROTETION Power-Supply onsiderations The ISL836 construction is typical of most single supply MOS analog switches, in that they have two supply pins: and. and drive the internal MOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL V maximum supply voltage provides plenty of room for the % tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. and also power the internal logic and level shifters. The level shifters convert the input logic levels to switched and signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch family is 1.8V MOS compatible (.5V and 1.4V) over a supply range of 2.V to 3.6V (See Figure 17). At 3.6V the V IH level is about 1.27V. This is still below the 1.8V MOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. High-Frequency Performance In 5 systems, the signal response is reasonably flat even past 3MHz with a -3dB bandwidth of 4MHz (See Figure 15). The frequency response is very consistent over a wide range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch s input to its output. Off Isolation is the resistance to this feedthrough, while rosstalk indicates the amount of feedthrough from one switch to another. Figure 16 details the high Off Isolation and rosstalk rejection provided by this part. At khz, Off Isolation is about 68dB in 5 systems, decreasing approximately 2dB per decade as frequency increases. Higher load impedances decrease Off Isolation and rosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. FN64 Rev 3. Page 7 of 11

8 Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and or. Typical Performance urves T A = 25, Unless Otherwise Specified.45 I = ma.35 = 2.7V I = ma R ON ( ) = 1.8V R ON ( ) = 2.7V.2-4 = 3V = 3.6V V (V) FIGURE. ON RESISTANE vs SUPPLY VOLTAGE vs SWITH VOLTAGE V (V) FIGURE. ON RESISTANE vs SWITH VOLTAGE = 1.8V I = ma 5 R ON ( ).4.35 Q (p) -5 = 1.8V = 3V V (V) FIGURE 11. ON RESISTANE vs SWITH VOLTAGE V (V) FIGURE 12. HARGE JETION vs SWITH VOLTAGE FN64 Rev 3. Page 8 of 11

9 Typical Performance urves T A = 25, Unless Otherwise Specified (ontinued) t ON (ns) t OFF (ns) (V) FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE (V) FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE NORMALIZED GA (db) = 3V GA -2 PHASE R L = 5 V =.2V P-P to 2V P-P 1 6 FREQUENY (MHz) FIGURE 15. FREQUENY RESPONSE PHASE (DEGREES) ROSSTALK (db) - = 3V ISOLATION -7-8 ROSSTALK K K K 1M M M 5M FREQUENY (Hz) FIGURE 16. ROSSTALK AND OFF ISOLATION OFF ISOLATION (db) V H AND V L (V) V H (V) V L FIGURE 17. DIGITAL SWITHG POT vs SUPPLY VOLTAGE Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): (QFN paddle connection: to ground or float) TRANSISTOR OUNT: 228 PROESS: Si Gate MOS FN64 Rev 3. Page of 11

10 Thin Shrink Small Outline Plastic Packages (TSSOP) N DEX AREA (.2) e D.(.4) M A M E1 -B- -Ab -- SEATG PLANE A B S E.25(.) M B A1 NOTES: 1. These package dimensions are within allowable dimensions of JEDE MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.15mm (.6 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only.. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch).. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. (Angles in degrees) GAUGE PLANE.(.4).25. A2 M L c M LEAD TH SHRK SMALL OUTLE PLASTI PAKAGE HES MILLIMETERS SYMBOL M MAX M MAX NOTES A A A b c D E e.26 BS.65 BS - E L N o 8 o o 8 o - Rev. 1 2/2 opyright Intersil Americas LL 24. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO1 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN64 Rev 3. Page of 11

11 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 6 DEX AREA A 4X X.15 B 2X.15 A SEATG PLANE 4X P (DATUM B) (DATUM A) 6 DEX AREA 4X P NX L 8 L N N e D D1 D2 D2 2 D/2 D1/2 TOP VIEW SIDE VIEW NX b 5 (Nd-1)Xe REF. N BOTTOM VIEW 5 NX b L1 2X.15 A E1/2 E/2 A. M A B A3 NX k A2 8 E2/2 SETION "-" L A1 E2 A1 E1 7 8 E B 2X.15 B.8 (Ne-1)Xe REF. L / / ORNER OPTION 4X. L1 L L16.3x3 16 LEAD QUAD FLAT NO-LEAD PLASTI PAKAGE MILLIMETERS SYMBOL M NOMAL MAX NOTES A A A A3.2 REF b , 8 D 3. BS - D BS D , 8, E 3. BS - E BS E , 8, e.5 BS - k L N 16 2 Nd 4 3 Ne 4 3 P Rev. 1 6/4 NOTES: 1. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between.15mm and.3mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PB Land Pattern Design efforts, see Intersil Technical Brief TB38.. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.. ompliant to JEDE MO-22VEED-2 Issue, except for the E2 and D2 MAX dimension. e TERMAL TIP FOR ODD TERMAL/SIDE e FOR EVEN TERMAL/SIDE FN64 Rev 3. Page 11 of 11