ISL43143, ISL43144, ISL43145

Transcription

1 ISL43143, ISL43144, ISL43145 Data Sheet FN637.3 Low-Voltage, Single and Dual Supply, Quad SPST, High Performance Analog Switches The Intersil ISL43143 ISL43145 devices are MOS, precision, quad SPST analog switches designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. Targeted applications include battery powered equipment that benefit from the devices low power consumption (<1µW), low leakage currents (5nA max), and fast switching speeds (t ON = 52ns, t OFF = 4ns). A 5Ω maximum R ON flatness ensures signal fidelity, while channel-to-channel mismatch is guaranteed to be less than 2Ω. The ISL43143/ISL43144/ISL43145 are quad single-pole/ single-throw (SPST) devices. The ISL43143 has four normally closed (N) switches; the ISL43144 has four normally open (NO) switches; the ISL43145 has two NO and two N switches and can be used as a dual SPDT, or a dual 2:1 multiplexer. Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANE ISL43143 ISL43144 ISL43145 Number of Switches onfiguration All N All NO 2 N/2 NO ±4.5V R ON 18Ω 18Ω 18Ω ±4.5V t ON /t OFF 52ns/4ns 52ns/4ns 52ns/4ns.8V R ON 14Ω 14Ω 14Ω.8V t ON /t OFF 4ns/27ns 4ns/27ns 4ns/27ns 4.5V R ON 3Ω 3Ω 3Ω 4.5V t ON /t OFF 64ns/29ns 64ns/29ns 64ns/29ns 3V R ON 51Ω 51Ω 51Ω 3V t ON /t OFF 1ns/ns 1ns/ns 1ns/ns Packages 16 Ld TSSOP, 16Ld QFN 4x4 Features Fully Specified for % Tolerances at V S = ±5V and = 12V, 5V and 3.3V Four Separately ontrolled SPST Switches Pin ompatible with DG411/DG412/DG413 ON Resistance (R ON Max.) Ω R ON Matching Between hannels <1Ω Low Power onsumption (P D ) <1µW Low Off Leakage urrent (Max at ) nA Fast Switching Action - t ON ns - t OFF ns Minimum V ESD Protection per Method 3.7 TTL, MOS ompatible Pb-Free Plus Anneal Available (RoHS ompliant) Applications Battery Powered, Handheld, and Portable Equipment - Barcode Scanners - Laptops, Notebooks, Palmtops ommunications Systems - Radios - XDSL and PBX / PABX - RF Tee Switches - Base Stations Test Equipment - Medical Ultrasound - Electrocardiograph - ATE Audio and Video Switching General Purpose ircuits - +3V/+5V DAs and ADs - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing Related Literature Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) AN557 Recommended Test Procedures for Analog Switches 1 AUTION: These devices are sensitive to electrostatic discharge; follow proper I Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. opyright Intersil Americas Inc All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Pinouts (Note 1) ISL43143 (TSSOP) TOP VIEW ISL43143 (QFN) TOP VIEW OM1 IN1 OM2 IN1 OM1 N OM2 N2 N N N.. 3 N.. N N3 N4 4 9 N3 OM4 IN OM3 IN OM4 IN4 IN3 OM3 ISL43144 (TSSOP) TOP VIEW ISL43144 (QFN) TOP VIEW IN1 NO1 OM NO2 OM2 OM1 1 NO1 IN1 NO OM OM4 NO4 IN N.. OM3 NO3 IN3 OM NO4 IN4 IN3 NO3 9 N.. OM3 ISL43145 (TSSOP) TOP VIEW ISL43145 (QFN) TOP VIEW IN1 NO1 OM OM2 N2 OM1 1 2 NO1 IN1 OM N N.. 3 N.. OM4 NO4 IN N3 OM3 IN3 OM NO4 IN4 IN3 OM3 9 N3 NOTE: 1. Switches Shown for Logic Input. 2 FN637.3

3 Truth Table ISL43143 ISL43144 ISL43145 LOGI SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3 ON OFF OFF ON 1 OFF ON ON OFF Ordering Information PART NO.* PART MARKING TEMP. RANGE ( ) PAKAGE PKG. DWG. # ISL43143IV 43143IV -4 to Ld TSSOP M ISL43143IVZ (Note 2) 43143IVZ -4 to Ld TSSOP (Pb-free) M NOTE: Logic.8V. Logic 1 2.4V. ISL43143IR 43143IR -4 to Ld QFN L16.4x4 Pin Descriptions PIN FUNTION Positive Power Supply Input Negative Power Supply Input. onnect to for Single Supply onfigurations. IN OM NO N N.. Ground onnection Digital ontrol Input Analog Switch ommon Pin Analog Switch Normally Open Pin Analog Switch Normally losed Pin No Internal onnection ISL43143IRZ (Note 2) 43143IRZ -4 to Ld QFN (Pb-free) L16.4x4 ISL43144IV 43144IV -4 to Ld TSSOP M ISL43144IVZ (Note 2) 43144IVZ -4 to Ld TSSOP (Pb-free) M ISL43144IR 43144IR -4 to Ld QFN L16.4x4 ISL43144IRZ (Note 2) 43144IRZ -4 to Ld QFN (Pb-free) L16.4x4 ISL43145IV 43145IV -4 to Ld TSSOP M ISL43145IVZ (Note 2) 43145IVZ -4 to Ld TSSOP (Pb-free) M ISL43145IR 43145IR -4 to Ld QFN L16.4x4 ISL43145IRZ (Note 2) 43145IRZ -4 to Ld QFN (Pb-free) L16.4x4 *Most surface mount devices are available on tape and reel; add -T to suffix. NOTE: 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-. 3 FN637.3

4 Absolute Maximum Ratings to tov to tov to to.3v All Other Pins (Note 3) (() -.3V) to (() +.3V) ontinuous urrent (Any Terminal) mA Peak urrent, IN, NO, N, or OM (Pulsed 1ms, % Duty ycle, Max) ma ESD Rating (Per MIL-STD-883 Method 3) >2kV Operating onditions Temperature Range ISL4314XIX to Thermal Information Thermal Resistance (Typical) θ JA ( /W) 16 Ld TSSOP Package (Note 4) Ld QFN Package (Note 5) Maximum Junction Temperature (Plastic Package) Moisture Sensitivity (See Technical Brief TB363) All Packages Level 1 Maximum Storage Temperature Range to 1 Maximum Lead Temperature (Soldering s) (TSSOP - Lead Tips Only) AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Signals on N, NO, OM, or IN exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 4. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θ JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB379 and Tech Brief TB389. Electrical Specifications: ±5V Supply Test onditions: V SUPPLY = ±4.5V to ±5.5V, = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified TEST ONDITIONS TEMP ( ) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON V S = ±4.5V, I OM = ma, V NO or V N = ±3.5V, Ω See Figure 5 Full Ω R ON Matching Between hannels, V S = ±4.5V, I OM = ma, V NO or V N = ±3V Ω R ON Full Ω R ON Flatness, R FLAT(ON) V S = ±4.5V, I OM = ma, V NO or V N = V, ±3V, Ω Note 8 Full Ω NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OM OFF Leakage urrent, I OM(OFF) V S = ±5.5V, V OM = ±4.5V, V NO or V N = +4.5V, Note 7 V S = ±5.5V, V OM = ±4.5V, V NO or V N = +4.5V, Note na na OM ON Leakage urrent, V S = ±5.5V, V OM = V NO or V N = ±4.5V, Note na I OM(ON) Full -5-5 na DIGITAL HARATERISTIS Input Voltage High, V INH Full V Input Voltage Low, V INL Full V Input urrent, I INH, I INL V S = ±5.5V, V IN = V or DYNAMI HARATERISTIS Turn-ON Time, t ON V S = ±4.5V, V NO or V N = ±3V, R L = 3Ω, L = 35pF, ns V IN = to 3V, See Figure 1 Full ns Turn-OFF Time, t OFF V S = ±4.5V, V NO or V N = ±3V, R L = 3Ω, L = 35pF, 25-4 ns V IN = to 3V, See Figure 1 Full ns Break-Before-Make Time Delay (ISL43145 only), t D V S = ±5.5V, V NO or V N = ±3V, R L = 3Ω, L = 35pF, V IN = to 3V, See Figure 3 Full ns harge Injection, Q L = 1.nF, V G = V, R G = Ω, See Figure p NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = V, See Figure pf 4 FN637.3

5 Electrical Specifications: ±5V Supply Test onditions: V SUPPLY = ±4.5V to ±5.5V, = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified (ontinued) OM OFF apacitance, f = 1MHz, V NO or V N = V OM = V, See Figure pf OM(OFF) OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V, See Figure pf OFF Isolation R L = Ω, L = pf, f = 1MHz, db rosstalk, Note 9 V NO or V N = 1V RMS, See Figures 4 and db Power Supply Rejection Ratio R L = Ω, L = 5pF, f = 1MHz db POWER SUPPLY HARATERISTIS Power Supply Range Full ±2 - ±6 V Positive Supply urrent, I+ V S = ±5.5V, V IN = V or, Switch On or Off µa Negative Supply urrent, I µa NOTES: 6. V IN = Input voltage to perform proper function. 7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 8. Leakage parameter is % tested at high temp, and guaranteed by correlation at. 9. Flatness is defined as the delta between the maximum and minimum R ON values over the specified voltage range.. Between any two switches. Electrical Specifications: 5V Supply Test onditions: = +4.5V to +5.5V, = = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified TEST ONDITIONS TEMP ( ) MIN (NOTE 6) TYP MAX (NOTE 6) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON = 4.5V, I OM = 1.mA, V NO or V N = 3.5V, Ω See Figure 5 Full - - Ω R ON Matching Between hannels, = 4.5V, I OM = 1.mA, V NO or V N = 3V Ω R ON Full Ω R ON Flatness, R FLAT(ON) = 5.5V, I OM = 1.mA, V NO or V N = 1V, 2V, 3V, Ω Note 8 Full Ω NO or N OFF Leakage urrent, = 5.5V, V OM = 1V, 4.5V, V NO or V N = 4.5V, 1V, na I NO(OFF) or I N(OFF) Note 7 OM OFF Leakage urrent, = 5.5V, V OM = 1V, 4.5V, V NO or V N = 4.5V, 1V, na I OM(OFF) Note 7 OM ON Leakage urrent, = 5.5V, V OM = V NO or V N = 1V, 4.5V, Note na I OM(ON) Full -5-5 na DIGITAL HARATERISTIS Input Voltage High, V INH Full V Input Voltage Low, V INL Full V Input urrent, I INH, I INL = 5.5V, V IN = V or DYNAMI HARATERISTIS Turn-ON Time, t ON = 4.5V, V NO or V N = 3V, R L = 3Ω, L = 35pF, ns V IN = to 3V, See Figure 1 Full ns Turn-OFF Time, t OFF = 4.5V, V NO or V N = 3V, R L = 3Ω, L = 35pF, ns V IN = to 3V, See Figure 1 Full ns Break-Before-Make Time Delay (ISL43145 only), t D TEST ONDITIONS = 5.5V, V NO or V N = 3V, R L = 3Ω, L = 35pF, V IN = to 3V, See Figure 3 TEMP ( ) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS Full 39 - ns 5 FN637.3

6 Electrical Specifications: 5V Supply Test onditions: = +4.5V to +5.5V, = = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified (ontinued) TEMP MIN MAX TEST ONDITIONS ( ) (NOTE 6) TYP (NOTE 6) UNITS harge Injection, Q L = 1.nF, V G = V, R G = Ω, See Figure p NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = V, See Figure pf OM OFF apacitance, f = 1MHz, V NO or V N = V OM = V, See Figure pf OM(OFF) OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V, See Figure pf OFF Isolation R L = Ω, L = pf, f = 1MHz, db rosstalk, Note 9 V NO or V N = 1V RMS, See Figures 4 and db Power Supply Rejection Ratio R L = Ω, L = 5pF, f = 1MHz db POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 5.5V, V IN = V or, Switch On or Off µa Negative Supply urrent, I µa Electrical Specifications: 3.3V Supply Test onditions: = +3.V to +3.6V, = = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified TEST ONDITIONS TEMP ( ) MIN (NOTE 6) TYP MAX (NOTE 6) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON = 3V, I OM = 1.mA, V NO or V N = 1.5V Ω See Figure 5 Full Ω R ON Matching Between hannels, = 3V, I OM = 1.mA, V NO or V N = 1.5V Ω R ON Full Ω R ON Flatness, R FLAT(ON) = 3V, I OM = 1.mA, V NO or V N =.5V, 1.5V, Ω Note 8 Full Ω NO or N OFF Leakage urrent, = 3.6V, V OM = 1V, 3V, V NO or V N = 3V, 1V, na I NO(OFF) or I N(OFF) Note 7 OM OFF Leakage urrent, = 3.6V, V OM = 1V, 3V, V NO or V N = 3V, 1V, na I OM(OFF) Note 7 OM ON Leakage urrent, = 3.6V, V OM = V NO or V N = 1V, 3V, Note na I OM(ON) Full -5-5 na DIGITAL HARATERISTIS Input Voltage High, V INH Full V Input Voltage Low, V INL Full V Input urrent, I INH, I INL = 3.6V, V IN = V or DYNAMI HARATERISTIS Turn-ON Time, t ON = 3.V, V NO or V N = 1.5V, R L = 3Ω, L = 35pF, ns V IN = to 3V, See Figure 1 Full ns Turn-OFF Time, t OFF = 3.V, V NO or V N = 1.5V, R L = 3Ω, L = 35pF, 25-6 ns V IN = to 3V, See Figure 1 Full ns Break-Before-Make Time Delay = 3.6V, V NO or V N = 1.5V, R L = 3Ω, L = 35pF, Full ns (ISL43145 only), t D V IN = to 3V, See Figure 3 harge Injection, Q L = 1.nF, V G = V, R G = Ω, See Figure p NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = V, See Figure pf OM OFF apacitance, f = 1MHz, V NO or V N = V OM = V, See Figure pf OM(OFF) OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V, See Figure pf 6 FN637.3

7 Electrical Specifications: 3.3V Supply Test onditions: = +3.V to +3.6V, = = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified (ontinued) TEMP MIN MAX TEST ONDITIONS ( ) (NOTE 6) TYP (NOTE 6) UNITS OFF Isolation R L = Ω, L = pf, f = 1MHz, db rosstalk, Note 9 V NO or V N = 1V RMS, See Figures 4 and db Power Supply Rejection Ratio R L = Ω, L = 5pF, f = 1MHz db POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 3.6V, V IN = V or, Switch On or Off µa Negative Supply urrent, I µa Electrical Specifications: 12V Supply Test onditions: = +.8V to +13.2V, = = V, V INH = 3.V, V INL =.8V (Note 5), Unless Otherwise Specified TEST ONDITIONS TEMP ( ) MIN (NOTE 6) TYP MAX (NOTE 6) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON =.8V, I OM = 1.mA, V NO or V N = 9V Ω See Figure 5 Full Ω R ON Matching Between hannels, =.8V, I OM = 1.mA, V NO or V N = 9V Ω R ON Full Ω R ON Flatness, R FLAT(ON) = 13.2V, I OM = 1.mA, V NO or V N = 3V, 6V, 9V, Ω Note 8 Full Ω NO or N OFF Leakage urrent, = 13V, V OM = 1V, 12V, V NO or V N = 12V, 1V, na I NO(OFF) or I N(OFF) Note 7 OM OFF Leakage urrent, = 13V, V OM = 1V, 12V, V NO or V N = 12V, 1V, na I OM(OFF) Note 7 OM ON Leakage urrent, = 13V, V OM = V NO or V N = 1V, 12V, Note na I OM(ON) Full -5-5 na DIGITAL HARATERISTIS Input Voltage High, V INH Full V Input Voltage Low, V INL Full V Input urrent, I INH, I INL = 13V, V IN = V or DYNAMI HARATERISTIS Turn-ON Time, t ON =.8V, V NO or V N = V, R L = 3Ω, L = 35pF, 25-4 ns V IN = to 3V, See Figure 1 Full ns Turn-OFF Time, t OFF =.8V, V NO or V N = V, R L = 3Ω, L = 35pF, ns V IN = to 3V, See Figure 1 Full ns Break-Before-Make Time Delay (ISL43145 only), t D = 13.2V, V NO or V N = V, R L = 3Ω, L = 35pF, V IN = to 3V, See Figure 3 Full 5 - ns harge Injection, Q L = 1.nF, V G = V, R G = Ω, See Figure p NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = V, See Figure pf OM OFF apacitance, f = 1MHz, V NO or V N = V OM = V, See Figure pf OM(OFF) OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V, See Figure pf OFF Isolation R L = Ω, L = pf, f = 1MHz, db rosstalk, Note 9 V NO or V N = 1V RMS, See Figures 4 and db Power Supply Rejection Ratio R L = Ω, L = 5pF, f = 1MHz db 7 FN637.3

8 Electrical Specifications: 12V Supply Test onditions: = +.8V to +13.2V, = = V, V INH = 3.V, V INL =.8V (Note 5), Unless Otherwise Specified (ontinued) TEMP MIN MAX TEST ONDITIONS ( ) (NOTE 6) TYP (NOTE 6) UNITS POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 13V, V IN = V or, Switch On or Off µa Negative Supply urrent, I µa Test ircuits and Waveforms LOGI SWITH SWITH OUTPUT 3V V V NX V % t ON t OFF 9% V OUT t r < ns t f < ns 9% Logic input waveform is inverted for switches that have the opposite logic sense. V NX SWITH LOGI NO or N IN OM V OUT R L 3Ω Repeat test for all switches. L includes fixture and stray capacitance. R L V OUT = V (NO or N) R L + R ( ON) L 35pF FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITHING TIMES FIGURE 1B. TEST IRUIT SWITH OUTPUT V OUT V OUT R G OM NO or N V OUT LOGI ON OFF ON 3V V V G IN L Q = V OUT x L LOGI Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. HARGE INJETION Repeat test for all switches. L includes fixture and stray capacitance. FIGURE 2B. TEST IRUIT 8 FN637.3

9 Test ircuits and Waveforms (ontinued) LOGI SWITH OUTPUT V OUT1 3V V V 9% 9% V NX NO1 N2 IN1 V OUT1 OM1 V OUT2 R L1 L1 OM2 3Ω 35pF R L2 L2 3Ω 35pF SWITH OUTPUT V OUT2 V 9% 9% LOGI t D t D L includes fixture and stray capacitance. Reconfigure accordingly to test SW3 and SW4. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST IRUIT FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL43145 ONLY) SIGNAL GENERATOR NO or N R ON = V 1 /1mA NO or N V NX IN V or 2.4V 1mA V 1 IN.8V or 2.4V ANALYZER R L OM OM Repeat test for all switches. Repeat test for all switches. FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE 5. R ON TEST IRUIT SIGNAL GENERATOR NO1 or N1 OM1 Ω NO or N V or 2.4V V or 2.4V IMPEDANE ANALYZER IN V or 2.4V ANALYZER R L OM2 NO2 or N2 NO ONNETION OM FIGURE 6. ROSSTALK TEST IRUIT FIGURE 7. APAITANE TEST IRUIT 9 FN637.3

10 Detailed Description The ISL43143 ISL43145 quad analog switches offer precise switching capability from a bipolar ±2V to ±6V or a single 2V to 12V supply with low on-resistance (18Ω) and high speed switching (t ON =52ns, t OFF = 4ns). The devices are especially well suited for portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (1µW), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high OFF isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection As with any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (see Figure 8). To prevent forward biasing these diodes, and must be applied before any input signals, and input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low R ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR IN X V NO or N FIGURE 8. OVERVOLTAGE PROTETION OPTIONAL PROTETION DIODE V OM OPTIONAL PROTETION DIODE Power-Supply onsiderations The ISL4314X construction is typical of most MOS analog switches, in that they have three supply pins:,, and. and drive the internal MOS switches and set their analog voltage limits, so there are no connections between the analog signal path and. Unlike switches with a 13V maximum supply voltage, the ISL4314X V maximum supply voltage provides plenty of room for the % tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies, and bipolar supplies need not be symmetrical. The minimum recommended supply voltage is 2V or ±2V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance urves for details. and power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched and signals to drive the analog switch gate terminals, so switch parameters - especially R ON - are strong functions of both supplies. Logic-Level Thresholds and power the internal logic stages, so has no affect on logic thresholds. This switch family is TTL compatible (.8V and 2.4V) over a supply range of 2.5V to V (see Figure 17). At 12V the V IH level is about 2.8V, so for best results use a logic family the provides a V OH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails (see Figure 18). Driving the digital input signals from to with a fast transition time minimizes power dissipation. The ISL43143-ISL43145 switches have been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (V to ). For example driving the device with 3V logic while operating with dual or single 5V supplies the device draws only µa of current (see Figure 18 for V IN = 3V). Similiar devices of competitors can draw 8 times this amount of current. High-Frequency Performance In Ω systems, signal response is reasonably flat even past MHz (see Figure 19). Figure 19 also illustrates that the frequency response is very consistent over a wide range, and for varying analog signal levels. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch s input to its output. OFF Isolation is the resistance to this feedthrough, while rosstalk indicates the amount of feedthrough from one switch to another. Figure details the high OFF Isolation and FN637.3

11 rosstalk rejection provided by this family. At MHz, OFF isolation is about db in Ω systems, decreasing approximately db per decade as frequency increases. Higher load impedances decrease OFF Isolation and rosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and. Typical Performance urves T A =, Unless Otherwise Specified R ON (Ω) 25 = -5V V OM = () - 1V I OM = 1mA 35 3 = -3V 25 1 = V (V) FIGURE 9. ON RESISTANE vs POSITIVE SUPPLY VOLTAGE R ON (Ω) 7 6 = 3V I OM = 1mA = V = 5V 3 = V = 12V 16 = V V OM (V) FIGURE. ON RESISTANE vs SWITH VOLTAGE R ON (Ω) I OM = 1mA V S = ±2V V S = ±5V V S = ±3V V OM (V) FIGURE 11. ON RESISTANE vs SWITH VOLTAGE Q (p) 5-5 V S = ±5V = 5V = 3V V OM (V) = 12V FIGURE 12. HARGE INJETION vs SWITH VOLTAGE 11 FN637.3

12 Typical Performance urves T A =, Unless Otherwise Specified (ontinued) 3 V OM = () - 1V V OM = () - 1V 2 = V 4 = V t ON (ns) 1 t OFF (ns) (V) FIGURE 13. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE t ON (ns) 3 2 = -5V V OM = () - 1V 1 2 = -3V (V) FIGURE. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE (V) FIGURE 14. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE t OFF (ns) = -5V V OM = () - 1V = -3V (V) FIGURE 16. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE V INH 7 6 = -5V to V = +5V 1.5 V INH AND V INL (V) V INL = V to -5V I+ (µa) = V to -5V (V) FIGURE 17. DIGITAL SWITHING POINT vs POSITIVE SUPPLY VOLTAGE V IN (V) FIGURE 18. POSITIVE SUPPLY URRENT vs DIGITAL VOLTAGE 12 FN637.3

13 Typical Performance urves T A =, Unless Otherwise Specified (ontinued) NORMALIZED GAIN (db) 3-3 GAIN PHASE V S = ±2V or = 5V (V IN = 4V P-P ) V S = ±5V (V IN = 5V P-P ) V S = ±2V (V IN = 4V P-P ) = 5V (V IN = 4V P-P ) V S = ±5V (V IN = 5V P-P ) = 2.7V (V 135 IN = 2V P-P ) 18 R L = Ω 1 6 FREQUENY (MHz) = 2.7V (V IN = 2V P-P ) FIGURE 19. FREQUENY RESPONSE 45 9 PHASE (DEGREES) ROSSTALK (db) = 3V to 12V or V S = ±2V to ±5V R L = Ω ISOLATION k k k 1M M M M FREQUENY (Hz) ROSSTALK ALL HOSTILE ROSSTALK FIGURE. ROSSTALK AND OFF ISOLATION OFF ISOLATION (db) PSRR (db) 3 4 = 3V to 12V or V S = ±2V to ±5V R L = Ω V IN = 1V P-P -PSRR, SWITH ON Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: ISL43143: 9 ISL43144: 9 ISL43145: 9 PROESS: 6 7 -PSRR, SWITH OFF +PSRR, SWITH OFF +PSRR, SWITH ON Si Gate MOS.3 1 FREQUENY (MHz) FIGURE 21. ±PSRR vs FREQUENY 13 FN637.3

14 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTI PAKAGE (OMPLIANT TO JEDE MO-2-VGG ISSUE ) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A A A A3. REF 9 b , 8 D 4. BS - D BS 9 D , 8 E 4. BS - E BS 9 E , 8 e.65 BS - k L L N 16 2 Nd 4 3 Ne 4 3 P θ Rev. 5 5/4 NOTES: 1. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between.mm and.3mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PB Land Pattern Design efforts, see Intersil Technical Brief TB Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation.. Depending on the method of lead termination at the edge of the package, a maximum.mm pull back (L1) maybe present. L minus L1 to be equal to or greater than.3mm. 14 FN637.3

15 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA (.2) e D.(.4) M A M E1 -B- -Ab -- SEATING PLANE A B S E.25(.) M B A1 NOTES: 1. These package dimensions are within allowable dimensions of JEDE MO-3-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side. 4. Dimension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (.6 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch).. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. (Angles in degrees) α GAUGE PLANE.(.4).25. A2 M L c M LEAD THIN SHRINK SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b c D E e.26 BS.65 BS - E L N α o 8 o o 8 o - Rev. 1 2/2 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil orporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN637.3