DATASHEET ISL84521, ISL84522, ISL Features. Applications. Related Literature. Low-Voltage, Single and Dual Supply, Quad SPST, Analog Switches

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1 DATASHEET ISL84521, ISL84522, ISL84523 Low-Voltage, Single and Dual Supply, Quad SPST, Analog Switches FN631 Rev 4. The Intersil ISL84521, ISL84523, ISL84523 devices are MOS, precision, quad analog switches designed to operate from a single +2V to +12V supply or from a 2V to 6V supply. Targeted applications include battery powered equipment that benefit from the devices low power consumption (<1 W), low leakage currents (1nA max), and fast switching speeds (t ON = 45ns, t OFF = 15ns). A12 maximum R ON flatness ensures signal fidelity, while channel-to-channel mismatch is guaranteed to be less than 4. The ISL84521, ISL84522, ISL84523 are quad single-pole/ single-throw (SPST) devices. The ISL84521 has four normally closed (N) switches; the ISL84522 has four normally open (NO) switches; the ISL84523 has two NO and two N switches and can be used as a dual SPDT, or a dual 2:1 multiplexer. Table 1 summarizes the performance of this family. For higher performance, pin compatible versions and 3mm x 3mm Quad No-Lead Flatpack (QFN) package see the ISL4314, ISL43142 data sheet. TABLE 1. FEATURES AT A GLANE ISL84521 ISL84522 ISL84523 Number of Switches onfiguration All N All NO 2 N/2 NO 5V R ON V t ON /t OFF 45ns/15ns 45ns/15ns 45ns/15ns 5V R ON V t ON /t OFF 6ns/2ns 6ns/2ns 6ns/2ns 3V R ON V t ON /t OFF 12ns/4ns 12ns/4ns 12ns/4ns Packages 16 Ld SOI (N), 16 Ld TSSOP Features Drop-in Replacements for MAX MAX4523 Four Separately ontrolled SPST Switches Pin ompatible with DG411, DG412, DG413 ON Resistance (R ON Max.) R ON Matching Between hannels <1 Low Power onsumption (P D ) <1 W Low Leakage urrent (Max at 85 o ) nA Fast Switching Action - t ON ns - t OFF ns Break before Make Timing Minimum 2V ESD Protection per Method TTL, MOS ompatible Pb-free available Applications Battery Powered, Handheld, and Portable Equipment - ellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops ommunications Systems - Military Radios - RF Tee Switches Test Equipment - Ultrasound - Electrocardiograph Heads-Up Displays Audio and Video Switching General Purpose ircuits - +3V/+5V DAs and ADs - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing Related Literature Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches FN631 Rev 4. Page 1 of 13

2 Pinouts (Note 1) ISL84521 (SOI, TSSOP) TOP VIEW ISL84522 (SOI, TSSOP) TOP VIEW IN IN2 IN IN2 OM OM2 OM OM2 N N2 NO NO N N.. N N3 NO NO3 OM4 7 1 OM3 OM4 7 1 OM3 IN4 8 9 IN3 IN4 8 9 IN3 ISL84523 (SOI, TSSOP) TOP VIEW IN IN2 OM OM2 NO N N.. NO N3 OM4 7 1 OM3 IN4 8 9 IN3 NOTE: 1. Switches Shown for Logic Input. Truth Table LOGI NOTE: ISL84521 ISL84522 ISL84523 SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3 On Off Off On 1 Off On On Off Logic.8V. Logic 1 2.4V. Pin Descriptions PIN FUNTION Positive Power Supply Input Negative Power Supply Input. onnect to for Single Supply onfigurations. IN OM Ground onnection Digital ontrol Input Analog Switch ommon Pin Ordering Information PART NO. (Note 2) TEMP. RANGE ( o ) PAKAGE (RoHS ompliant) PKG. DWG. # ISL84521IBZ* -4 to Ld SOI (N) M16.15 ISL84521IVZ* -4 to Ld TSSOP M ISL84522IBZ* -4 to Ld SOI (N) M16.15 ISL84522IVZ* -4 to Ld TSSOP M ISL84523IBZ* No longer available, recommended replacement: ISL84524IUZ-T) -4 to Ld SOI (N) M16.15 ISL84523IVZ* No longer available, recommended replacement: ISL84524IUZ-T) *Add -T suffix to part number for tape and reel packaging. -4 to Ld TSSOP M NO N N.. Analog Switch Normally Open Pin Analog Switch Normally losed Pin No Internal onnection NOTE: 2. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J Std-2B. FN631 Rev 4. Page 2 of 13

3 Absolute Maximum Ratings to to15v to to15v to to.3v All Other Pins (Note 3) (() -.3V) to (() +.3V) ontinuous urrent (Any Terminal) mA Peak urrent, IN, NO, N, or OM (Pulsed 1ms, 1% Duty ycle, Max) mA ESD Rating (Per MIL-STD-883 Method 315) > 2kV Operating onditions Temperature Range ISL8452XIX o to 85 o Thermal Information Thermal Resistance (Typical, Note 4) JA ( o /W) 16 Ld SOI Package Ld TSSOP Package Maximum Junction Temperature (Plastic Package) o Moisture Sensitivity (See Technical Brief TB363) All Packages Level 1 Maximum Storage Temperature Range o to 1 o Maximum Lead Temperature (Soldering 1s) o (Lead Tips Only) AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Signals on N, NO, OM, or IN exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications +5V Supply Test onditions: V SUPPLY = 4.5V to 5.5V, = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( o ) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON V S = 5V, I OM = 1.mA, V NO or V N = 3V (Figure 5) Full R ON Matching Between hannels, V S = 5V, I OM = 1.mA, V NO or V N = 3V R ON Full R ON Flatness, R FLAT(ON) V S = 5V, I OM = 1.mA, V NO or V N = 3V (Note 8) Full NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OM OFF Leakage urrent, I OM(OFF) V S = 5.5V, V OM = 4.5V, V NO or V N = +4.5V (Note 7) V S = 5.5V, V OM = 4.5V, V NO or V N = +4.5V (Note 7) na Full -1-1 na na Full -1-1 na OM ON Leakage urrent, V S = 5.5V, V OM = V NO or V N = 4.5V (Note 7) na I OM(ON) Full -2-2 na DIGITAL HARATERISTIS Input Voltage High, V INH Full V Input Voltage Low, V INL Full V Input urrent, I INH, I INL V S = 5.5V, V IN = V or Full A DYNAMI HARATERISTIS Turn-ON Time, t ON V S = 4.5V, V NO or V N = 3V, R L = 3, L = 35pF, ns V IN = to 3V (Figure 1) Full - - ns Turn-OFF Time, t OFF V S = 4.5V, V NO or V N = 3V, R L = 3, L = 35pF, ns V IN = to 3V (Figure 1) Full ns Break-Before-Make Time Delay (ISL84523), t D V S = 5.5V, V NO or V N = 3V, R L = 3, L = 35pF, V IN = to 3V (Figure 3) ns harge Injection, Q L = 1.nF, V G = V, R G = (Figure 2) p NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = V (Figure 7) pf OM OFF apacitance, f = 1MHz, V NO or V N = V OM = V (Figure 7) pf OM(OFF) OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V (Figure 7) pf FN631 Rev 4. Page 3 of 13

4 Electrical Specifications +5V Supply Test onditions: V SUPPLY = 4.5V to 5.5V, = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified (ontinued) TEMP (NOTE 6) (NOTE 6) PARAMETER TEST ONDITIONS ( o ) MIN TYP MAX UNITS OFF Isolation R L =, L = 15pF, f = khz, 25 - >9 - db rosstalk, (Note 9) V NO or V N = 1V RMS, (See Figures 4 and 6) 25 - <-9 - db POWER SUPPLY HARATERISTIS Power Supply Range Full 2-6 V Positive Supply urrent, I+ V S = 5.5V, V IN = V or, Switch On or Off A Full -1-1 A Negative Supply urrent, I A Full -1-1 A NOTES: 5. V IN = Input voltage to perform proper function. 6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is % tested at high temp, and guaranteed by correlation at 25 o. 8. Flatness is defined as the delta between the maximum and minimum R ON values over the specified voltage range. 9. Between any two switches. Electrical Specifications 5V Supply Test onditions: = +4.5V to +5.5V, = = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( o ) MIN (NOTE 6) TYP MAX (NOTE 6) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON = 4.5V, I OM = 1.mA, V NO or V N = 3.5V (Figure 5) Full R ON Matching Between hannels, = 5V, I OM = 1.mA, V NO or V N = 3.5V R ON Full NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OM OFF Leakage urrent, I OM(OFF) = 5.5V, V OM = 1V, 4.5V, V NO or V N = 4.5V, 1V (Note 7) = 5.5V, V OM = 1V, 4.5V, V NO or V N = 4.5V, 1V (Note 7) na Full -1-1 na na Full -1-1 na OM ON Leakage urrent, = 5.5V, V OM = 1V, 4.5V (Note 7) na I OM(ON) Full -2-2 na DIGITAL HARATERISTIS Input Voltage High, V INH Full V Input Voltage Low, V INL Full V Input urrent, I INH, I INL = 5.5V, V IN = V or Full A DYNAMI HARATERISTIS Turn-ON Time, t ON = 4.5V, V NO or V N = 3V, R L = 3, L = 35pF, 25-6 ns V IN = to 3V (Figure 1) Full ns Turn-OFF Time, t OFF = 4.5V, V NO or V N = 3V, R L = 3, L = 35pF, 25-2 ns V IN = to 3V (Figure 1) Full ns Break-Before-Make Time Delay (ISL84523), t D = 5.5V, V NO or V N = 3V, R L = 3, L = 35pF, V IN = to 3V (Figure 3) ns harge Injection, Q L = 1.nF, V G = V, R G = Figure 2) p FN631 Rev 4. Page 4 of 13

5 Electrical Specifications 5V Supply Test onditions: = +4.5V to +5.5V, = = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified (ontinued) TEMP MIN MAX PARAMETER TEST ONDITIONS ( o ) (NOTE 6) TYP (NOTE 6) UNITS POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 5.5V, V IN = V or, Switch On or Off A Full -1-1 A Negative Supply urrent, I A Full -1-1 A Electrical Specifications 3V Supply Test onditions: = +2.7V to +3.6V, = = V, V INH = 2.4V, V INL =.8V (Note 5), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( o ) MIN (NOTE 6) TYP MAX (NOTE 6) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON = 2.7V, I OM =.1mA, V NO or V N = 1V Full DIGITAL HARATERISTIS Input Voltage High, V INH Full V Input Voltage Low, V INL Full V Input urrent, I INH, I INL = 3.6V, V IN = V or Full A DYNAMI HARATERISTIS Turn-ON Time, t ON = 2.7V, V NO or V N = 1.5V, R L = 3, L = 35pF, ns V IN = to (Figure 1) Full ns Turn-OFF Time, t OFF = 2.7V, V NO or V N = 1.5V, R L = 3, L = 35pF, ns V IN = to (Figure 1) Full - - ns Break-Before-Make Time Delay (ISL84523), t D = 3.6V, V NO or V N = 1.5V, R L = 3, L = 35pF, V IN = to 3V (Figure 3) ns harge Injection, Q L = 1.nF, V G = V, R G = Figure 2) p POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 3.6V, V IN = V or, Switch On or Off A Full -1-1 A Negative Supply urrent, I A Full -1-1 A Test ircuits and Waveforms LOGI SWITH SWITH OUTPUT 3V V V NX V % t ON t OFF 9% V OUT t r < 2ns t f < 2ns 9% Logic input waveform is inverted for switches that have the opposite logic sense. V NX SWITH LOGI NO OR N IN OM V OUT R L 3 Repeat test for all switches. L includes fixture and stray capacitance. R L V OUT = V (NO or N) R L + R ON L 35pF FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITHING TIMES FIGURE 1B. TEST IRUIT FN631 Rev 4. Page 5 of 13

6 Test ircuits and Waveforms (ontinued) SWITH OUTPUT V OUT V OUT R G NO OR N OM V OUT LOGI ON OFF ON 3V V V G IN L Q = V OUT x L LOGI Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. HARGE INJETION Repeat test for all switches. L includes fixture and stray capacitance. FIGURE 2B. TEST IRUIT LOGI 3V V V NX NO1 N2 IN1 OM1 OM2 V OUT2 R L1 3 V OUT1 L1 35pF SWITH OUTPUT V OUT1 SWITH OUTPUT V OUT2 V V 9% t D 9% t D 9% 9% LOGI IN2 L includes fixture and stray capacitance. R L2 3 L2 35pF Reconfigure accordingly to test SW3 and SW4. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST IRUIT FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL84523 ONLY) SIGNAL GENERATOR NO OR N R ON = V 1 /1mA NO OR N V NX IN V OR 2.4V 1mA V 1 IN.8V OR 2.4V ANALYZER OM OM R L Repeat test for all switches. FIGURE 4. OFF ISOLATION TEST IRUIT Repeat test for all switches. FIGURE 5. R ON TEST IRUIT FN631 Rev 4. Page 6 of 13

7 Test ircuits and Waveforms (ontinued) SIGNAL GENERATOR NO1 OR N1 OM1 NO OR N V or 2.4V IN2 IN2 V OR 2.4V IMPEDANE ANALYZER IN V OR 2.4V ANALYZER R L OM2 NO2 OR N2 NO ONNETION OM FIGURE 6. ROSSTALK TEST IRUIT Detailed Description The ISL84521, ISL84522, ISL84523 quad analog switches offer precise switching capability from a bipolar 2V to 6V or a single 2V to 12V supply with low on-resistance (65 ) and high speed switching (t ON = 45ns, t OFF = 15ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (1 W) and low leakage currents (1nA max). High frequency applications also benefit from the wide bandwidth, and the very high OFF isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection As with any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (Figure 8). To prevent forward biasing these diodes, and must be applied before any input signals, and input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low R ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (Figure 8). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is FIGURE 7. APAITANE TEST IRUIT unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR IN X V NO OR N FIGURE 8. OVERVOLTAGE PROTETION Power-Supply onsiderations The ISL8452X construction is typical of most MOS analog switches, in that they have three supply pins:,, and. and drive the internal MOS switches and set their analog voltage limits, so there are no connections between the analog signal path and. Unlike switches with a 13V maximum supply voltage, the ISL8452X 15V maximum supply voltage provides plenty of room for the 1% tolerance of 12V supplies ( 6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies, and bipolar supplies need not be symmetrical. The minimum recommended supply voltage is 2V or 2V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance urves for details. OPTIONAL PROTETION DIODE V OM OPTIONAL PROTETION DIODE FN631 Rev 4. Page 7 of 13

8 and power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched and signals to drive the analog switch gate terminals, so switch parameters - especially R ON - are strong functions of both supplies. Logic-Level Thresholds and power the internal logic stages, so has no affect on logic thresholds. This switch family is TTL compatible (.8V and 2.4V) over a supply range of 2.5V to 1V. At 12V the V IH level is about 2.7V, so for best results use a logic family the provides a V OH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. High-Frequency Performance In systems, signal response is reasonably flat even past 3MHz (Figure 15), with a small signal -3dB bandwidth in excess of 4MHz, and a large signal bandwidth exceeding 3MHz. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch s input to its output. OFF Isolation is the resistance to this feedthrough, while rosstalk indicates the amount of feedthrough from one switch to another. Figure 16 details the high OFF Isolation and rosstalk rejection provided by this family. At 1MHz, OFF isolation is about db in systems, decreasing approximately 2dB per decade as frequency increases. Higher load impedances decrease OFF Isolation and rosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and. Typical Performance urves T A = 25 o, Unless Otherwise Specified R ON ( ) o -4 o 25 o = -5V = V 85 o 25 o -4 o V OM = () - 1V I OM = 1mA (V) R ON ( ) 3 2 I OM = 1mA 85 o 2 25 o 1-4 o = 2.7V = V o o = 3.3V -4 o = V o = 5V = V o 8-4 o V OM (V) FIGURE 9. ON RESISTANE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANE vs SWITH VOLTAGE FN631 Rev 4. Page 8 of 13

9 Typical Performance urves T A = 25 o, Unless Otherwise Specified (ontinued) R ON ( ) I OM = 1mA 85 o 85 o 25 o -4 o V S = 2V V S = 3V 25 o -4 o Q (p) = 3.3V = 5V o V S = 5V 7 25 o -4 o V OM (V) V S = 5V V OM (V) FIGURE 11. ON RESISTANE vs SWITH VOLTAGE FIGURE 12. HARGE INJETION vs SWITH VOLTAGE t ON (ns) o = -5V V OM = () - 1V -4 o 25 o 85 o -4 o = V 85 o 25 o -4 o (V) t OFF (ns) o = -5V V OM = () - 1V -4 o 25 o 85 o -4 o = V 85 o 25 o -4 o (V) FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE FN631 Rev 4. Page 9 of 13

10 Typical Performance urves T A = 25 o, Unless Otherwise Specified (ontinued) NORMALIZED GAIN (db) V S = 5V 3 GAIN -3 PHASE R L = V IN =.2V P-P V IN = 5V P-P 45 V IN =.2V P-P 9 V IN = 5V P-P FREQUENY (MHz) FIGURE 15. FREQUENY RESPONSE 18 PHASE (DEGREES) ROSSTALK (db) = 3V to 12V or V S = 2V to 5V R L = ISOLATION k 1k k 1M 1M M M FREQUENY (Hz) ROSSTALK FIGURE 16. ROSSTALK AND OFF ISOLATION OFF ISOLATION (db) Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: ISL84521: 188 ISL84522: 188 ISL84523: 188 PROESS: Si Gate MOS FN631 Rev 4. Page 1 of 13

11 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION HANGE FN631.4 Updated Ordering Information table on page 2. Added Revision History and About Intersil sections. Updated Package Outline Drawing (POD) M with the latest version. hanges from Rev. 1 to Rev 2 are as follows: -onvert to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. About Intersil Intersil orporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN631 Rev 4. Page 11 of 13

12 Small Outline Plastic Packages (SOI) N INDEX AREA e D B.25(.1) M A M E -B- -A- -- SEATING PLANE A B S H.25(.1) M B A1.1(.4) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.14 inch) or greater above the seating plane, shall not exceed a maximum value of.61mm (.24 inch). 1. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. L M h x 45 M16.15 (JEDE MS-12-A ISSUE ) 16 LEAD NARROW BODY SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B D E e. BS 1.27 BS - H h L N Rev. 1 6/5 FN631 Rev 4. Page 12 of 13

13 Package Outline Drawing M LEAD THIN SHRINK SMALL OUTLINE PAKAGE (TSSOP) Rev 2, 5/1 A ± SEE DETAIL "X" ± PIN #1 I.D. MARK.2 B A B.9-.2 TOP VIEW END VIEW H REF SEATING PLANE.1 SIDE VIEW 1.2 MAX / M B A /-.1.5 MIN.15 MAX DETAIL "X" GAUGE PLANE -8.6 ± (1.45) NOTES: (5.65) (.65 TYP) (.35 TYP) TYPIAL REOMMENDED LAND PATTERN Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.15 per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed.25 per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y14.5M Dimension does not include dambar protrusion. Allowable protrusion shall be.8mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm. Dimension in ( ) are for reference only. onforms to JEDE MO-153. FN631 Rev 4. Page 13 of 13