ISL43210A (6 LD SOT-23) TOP VIEW COM GND

Transcription

1 DATASHEET ISL4321A Medium-Voltage, Single Supply, Single SPDT Analog Switch FN7876 Rev. The Intersil ISL4321A device is a precision, bidirectional, single SPDT analog switch designed to operate from a single +2.7V to +15V supply. Targeted applications include applications that require a +15V single supply such as 3D TV/Eyeware products and single supply +3.V/+5V battery powered equipment that benefit from the devices low power consumption (5µW), low leakage currents (1nA max), and fast switching speeds (t ON = 28ns, t OFF = ns). ell phones, for example, often face ASI functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This device may be used to mux-in additional functionality while reducing ASI design risk. It s small package alleviates board space limitations, making it an ideal solution. The ISL4321A is a single committed SPDT, which is perfect for use in 2-to-1 multiplexer applications. SW 1/SW 2 TABLE 1. FEATURES AT A GLANE Related Literature ISL4321A SPDT or 2x1 MUX 12V r ON 11Ω 12V t ON /t OFF 25ns/17ns 5V r ON 19Ω 5V t ON /t OFF 28ns/ns 3.3V r ON 32Ω 3.3V t ON /t OFF ns/ns Package 6 Ld SOT-23 Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches Features Fully specified at 12V, 5V, and 3.3V supplies for 1% tolerances ON-resistance (r ON ) Ω r ON matching between channels <1Ω Low charge injection p Single supply operation V to +15V Low leakage current nA Fast switching action - t ON ns - t OFF ns Guaranteed break-before-make switching Minimum V ESD protection per method 15.7 TTL, MOS compatible Available in 6 Ld SOT-23 package Pb-free (RoHS compliant) Applications Battery-powered, handheld, and portable equipment - ellular/mobile phones - Pagers - Laptops, notebooks, palmtops ommunications systems - Radios, ADSL Modems - PBX, PABX Test and measurement equipment - Ultrasound - omputerized Tomography (T) Scanner - Magnetic Resonance Image (MRI) - Positron Emission Tomography (PET) Scanner - Electrocardiograph Audio and Video switching - 3D TV - 3D Eyeware Various circuits - +3V/+5V DAs and ADs - Sample and hold circuits - Digital filters - Operational amplifier gain switching networks - High frequency analog switching - High speed multiplexing - Integrator reset circuits FN7876 Rev. Page 1 of 12

2 Pin onfiguration (Note 1) ISL4321A (6 LD SOT-23) TOP VIEW IN 1 6 NO 2 5 OM 3 4 N NOTE: 1. Switch Shown for Logic Input. Truth Table NOTE: LOGI PIN N ISL4321A PIN NO ON OFF 1 OFF ON Logic.8V. Logic 1 2.4V. Pin Descriptions PIN NAME PIN NUMBER FUNTION 2 System Power Supply Input (+2.7V to +15V) 3 Ground onnection IN 1 Digital ontrol Input OM 5 Analog Switch ommon Pin Ordering Information PART NUMBER (Notes 2, 3, 4) PART MARKING (Note 5) TEMP. RANGE ( ) PAKAGE (Pb-free) PKG. DWG. # ISL4321AIHZ-T 21A - to Ld SOT-23 P6.64 ISL4321AIHZ-T7A 21A - to Ld SOT-23 P6.64 NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 1% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL4321A. For more information on MSL please see techbrief TB The part marking is located on the bottom of the part. NO 6 Analog Switch Normally Open Pin N 4 Analog Switch Normally losed Pin FN7876 Rev. Page 2 of 12

3 Absolute Maximum Ratings to to 16.5V Input Voltages IN (Note 6) to (() +.3V) NO, N (Note 6) to (() +.3V) Output Voltages OM (Note 6) to (() +.3V) ontinuous urrent (Any Terminal) ma Peak urrent NO, N, or OM (Pulsed 1ms, 1% Duty ycle, Max) ma ESD Rating Human Body Model (Tested per JESD22-A114E) kV Machine Model (Tested per JESD22-A115-A) V Latch Up (Tested per JESD-78B; lass 2, Level A) mA Thermal Information Thermal Resistance (Typical) JA ( /W) J ( /W) 6 Ld SOT-23 Package (Notes 7, 8) Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +15 Pb-Free Reflow Profile see link below Operating onditions Temperature Range to Maximum Operating Voltage V AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. Signals on N, NO, OM, or IN exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. For J, the case temp location is taken at the package top center. Electrical Specifications - 12V Supply Test onditions: = +1.8V to +15V, = V, V INH = 4V, V INL =.8V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, to. PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON = 1.8V, I OM = 1.mA, V NO or V N = 1V (see Figure 5) Ω Full Ω r ON Matching Between hannels, r ON = 1.8V, I OM = 1.mA, V NO or V N = 1V Ω Full Ω r ON Flatness, R FLAT(ON) = 1.8V, I OM = 1.mA, V NO or V N = 3V, 6V, 9V (Note 12) Ω Full Ω NO or N OFF Leakage urrent, I NO(OFF) = 15V, V OM = 1V, 12V, V NO or V N = 12V, 1V na or I N(OFF) Full -5-5 na OM OFF Leakage urrent, I OM(OFF) = 15V, V OM = 12V, 1V, V NO or V N = 1V, 12V na Full -5-5 na OM ON Leakage urrent, I OM(ON) DYNAMI HARATERISTIS Turn-ON Time, t ON Turn-OFF Time, t OFF = 15V, V OM = 1V, 12V, or V NO or V N = 1V, 12V or floating V NO or V N = 1V, R L = 1kΩ, L = 35pF, V IN =Vto 4V (see Figure 1) V NO or V N = 1V, R L = 1kΩ, L = 35pF, V IN = V to 4V (see Figure 1) na Full -1-1 na ns Full ns ns Full ns Break-Before-Make Time Delay, t D R L = Ω, L = 35pF, V NO or V N = 1V, V IN = V to 4V (see Figure 3) Full ns harge Injection, Q L = 1.nF, V G = V, R G = Ω (see Figure 2) p OFF Isolation R L = 5Ω, L = 5pF, f = 1MHz (see Figure 4) db FN7876 Rev. Page 3 of 12

4 Electrical Specifications - 12V Supply Test onditions: = +1.8V to +15V, = V, V INH = 4V, V INL =.8V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, to. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS rosstalk (hannel-to-hannel) R L = 5Ω, L = 5pF, f = 1MHz (see Figure 6) db Power Supply Rejection Ratio R L = 5Ω, L = 5pF, f = 1MHz db NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = V (see Figure 7) pf OM OFF apacitance, OM(OFF) f = 1MHz, V NO or V N = V OM = V (see Figure 7) pf OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V (See Figure 7) pf POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 15V, V IN = V or, all channels on or off Full µa DIGITAL HARATERISTIS Input Voltage Low, V INL Full V Input Voltage High, V INH Full V Input urrent, I INH, I INL = 15V, V IN = V or Full -1-1 µa Electrical Specifications - 5V Supply Test onditions: = +4.5V to +5.5V, = V, V INH = 2.4V, V INL =.8V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, to. PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON = 4.5V, I OM = 1.mA, V NO or V N = 3.5V (See Figure 5) Ω Full - 23 Ω r ON Matching Between hannels, r ON = 5V, I OM = 1.mA, V NO or V N = 3.5V Ω Full Ω r ON Flatness, R FLAT(ON) = 5V, I OM = 1.mA, V NO or V N = 1V, 2V, 3V (Note 12) Full Ω NO or N OFF Leakage urrent, = 5.5V, V OM = 1V, 4.5V, V NO or V N = 4.5V, 1V na I NO(OFF) or I N(OFF) Full -5-5 na OM OFF Leakage urrent, I OM(OFF) = 5.5V, V OM = 4.5V, 1V, V NO or V N = 1V, 4.5V na Full -5-5 na OM ON Leakage urrent, I OM(ON) = 5.5V, V OM = 1V, 4.5V, or V NO or V N = 1V, 4.5V or Floating DYNAMI HARATERISTIS na Full -1-1 na Turn-ON Time, t ON Turn-OFF Time, t OFF V NO or V N = 3V, R L = 1kΩ, L = 35pF, V IN = V to 3V (See Figure 1) V NO or V N = 3V, R L = 1kΩ, L = 35pF, V IN = V to 3V (See Figure 1) ns Full - - ns ns Full - - ns Break-Before-Make Time Delay, t D R L = Ω, L = 35pF, V NO = V N = 3V, V IN = V to 3V (See Figure 3) Full ns harge Injection, Q L = 1.nF, V G = V, R G = Ω (See Figure 2) p OFF Isolation R L = 5Ω, L = 5pF, f = 1MHz (See Figure 4) db FN7876 Rev. Page 4 of 12

5 Electrical Specifications - 5V Supply Test onditions: = +4.5V to +5.5V, = V, V INH = 2.4V, V INL =.8V (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, to. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS Power Supply Rejection Ratio R L = 5Ω, L = 5pF, f = 1MHz db NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = V (See Figure 7) pf OM OFF apacitance, OM(OFF) f = 1MHz, V NO or V N = V OM = V (See Figure 7) pf OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V (See Figure 7) pf POWER SUPPLY HARATERISTIS Power Supply Range Full V Positive Supply urrent, I+ = 5.5V, V IN = V or, all channels on or off Full µa DIGITAL HARATERISTIS Input Voltage Low, V INL Full V Input Voltage High, V INH Full V Input urrent, I INH, I INL = 5.5V, V IN = V or Full -1-1 µa Electrical Specifications - 2.7V to 5.5V Supply Test onditions: = +3.V to +3.6V, = V, V INH = 2.4V, V INL =.8V (Note 9),Unless Otherwise Specified. Boldface limits apply over the operating temperature range, to. PARAMETER ANALOG SWITH HARATERISTIS TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON = 3V, I OM = 1.mA, V NO or V N = 1.5V Ω (see Figure 5) Full - 6 Ω r ON Matching Between hannels, r ON = 3.3V, I OM = 1.mA, V NO or V N = 1.5V Ω Full Ω r ON Flatness, R FLAT(ON) = 3.3V, I OM = 1.mA, V NO or V N =.5V, 1V, 1.5V Ω (Note 12) Full Ω NO or N OFF Leakage urrent, I NO(OFF) = 3.6V, V OM = 1V, 3V, V NO or V N = 3V, 1V na or I N(OFF) Full -5-5 na OM OFF Leakage urrent, I OM(OFF) = 3.6V, V OM = 3V, 1V, V NO or V N = 1V, 3V na Full -5-5 na OM ON Leakage urrent, I OM(ON) = 3.6V, V OM = 1V, 3V, or V NO or V N = 1V, 3V or na floating Full -1-1 na DYNAMI HARATERISTIS Turn-ON Time, t ON Turn-OFF Time, t OFF Break-Before-Make Time Delay, t D V NO or V N = 1.5V, R L = 1kΩ, L = 35pF, V IN = V to 3V (see Figure 1) V NO or V N = 1.5V, R L = 1kΩ, L = 35pF, V IN = V to 3V (see Figure 1) R L = Ω, L = 35pF, V NO or V N = 1.5V, V IN = V to 3V (see Figure 3) ns Full ns ns Full - - ns Full - - ns harge Injection, Q L = 1.nF, V G = V, R G = Ω (see Figure 2) p OFF Isolation R L = 5Ω, L = 5pF, f = 1MHz (see Figure 4) db Power Supply Rejection Ratio R L = 5Ω, L = 5pF, f = 1MHz db NO or N OFF apacitance, OFF f = 1MHz, V NO or V N = V OM = V (see Figure 7) pf FN7876 Rev. Page 5 of 12

6 Electrical Specifications - 2.7V to 5.5V Supply Test onditions: = +3.V to +3.6V, = V, V INH = 2.4V, V INL =.8V (Note 9),Unless Otherwise Specified. Boldface limits apply over the operating temperature range, to. (ontinued) PARAMETER OM OFF apacitance, OM(OFF) f = 1MHz, V NO or V N = V OM = V (see Figure 7) pf OM ON apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V (See Figure 7) pf POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 3.6V, V IN = V or, all channels on or off Full -1-1 µa DIGITAL HARATERISTIS TEST ONDITIONS Input Voltage Low, V INL Full V Input Voltage High, V INH Full V Input urrent, I INH, I INL = 3.6V, V IN = V or Full -1-1 µa NOTES: 9. V IN = input voltage to perform proper function. 1. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 11. ompliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 12. Limits established by characterization and are not production tested. Test ircuits and Waveforms TEMP ( ) MIN TYP MAX UNITS 3V OR 4V LOGI V 5% t r < ns t f < ns SWITH SWITH OUTPUT V NO V t OFF 9% V OUT 9% SWITH LOGI NO OR N IN OM R L 1kΩ V OUT L 35pF t ON Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITHING TIMES Repeat test for all switches. L includes fixture and stray capacitance. R L V OUT = V (NO or N) R L + r ON FIGURE 1B. TEST IRUIT SWITH OUTPUT V OUT LOGI ON V OUT OFF ON V V G R G NO OR N IN OM L V OUT Q = V OUT x L FIGURE 2A. MEASUREMENT POINTS LOGI FIGURE 2. HARGE INJETION FIGURE 2B. TEST IRUIT FN7876 Rev. Page 6 of 12

7 Test ircuits and Waveforms (ontinued) 3V OR 4V LOGI V SWITH OUTPUT V OUT V t D 9% V NX LOGI NO N IN OM R L Ω V OUT L 35pF L includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST IRUIT SIGNAL GENERATOR NO OR N r ON = V 1 /1mA NO OR N V NX IN X V OR V INH 1mA V 1 IN.8V OR V INH ANALYZER OM OM R L FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE 5. r ON TEST IRUIT SIGNAL GENERATOR NO1 OR N1 OM1 5Ω NO OR N V OR 2.4V IN 1 IN 2 V OR V INH IMPEDANE ANALYZER IN X V OR V INH ANALYZER R L OM2 NO2 OR N2 N OM FIGURE 6. ROSSTALK TEST IRUIT FIGURE 7. APAITANE TEST IRUIT FN7876 Rev. Page 7 of 12

8 Detailed Description The ISL4321A bidirectional, single SPDT analog switch offers precise switching capability from a single 2.7V to 15V supply with low ON-resistance (11Ω) and high speed operation. The device is especially well suited for 3D TV and 3D eyeware equipment thanks to the high single supply operating voltage (15V), low power consumption (27µW max), fast switching speed (t ON =25ns, t OFF = 17ns), and the tiny SOT-23 packaging. High frequency applications also benefit from the wide bandwidth and the very high off isolation rejection. Supply Sequencing and Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents that might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and (see Figure 8). To prevent forward biasing these diodes, must be applied before any input signals, and input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low r ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR IN X V NO OR N Power-Supply onsiderations The ISL4321A construction is typical of most MOS analog switches, except that it has only two supply pins: and. and drive the internal MOS switches and set their analog voltage limits. Unlike switches with a 13V absolute maximum voltage, the ISL4321A 16.5V absolute maximum supply voltage provides plenty of room for the 1% tolerance of 15V supplies, as well as room for overshoot and noise spikes. OPTIONAL PROTETION DIODE V OM OPTIONAL PROTETION DIODE FIGURE 8. OVERVOLTAGE PROTETION The minimum recommended supply voltage is 2.7V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the Electrical Specification tables beginning on page 3 and Typical Performance urves beginning on page 9 for details. and also power the internal logic and level shifter. The level shifter converts the input logic levels to switch and signals to drive the analog switch gate terminals. This device cannot be operated with bipolar supplies because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch is TTL compatible (.8V and 2.4V) over a supply range of 3V to 11V (see Figure 15). At 12V the V IH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family the provides a V OH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. High-Frequency Performance In 5Ω systems, signal response is reasonably flat even past MHz (see Figure 16). Figure 16 also illustrates that the frequency response is very consistent over a wide range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch s input to its output. Off isolation is the resistance to this feed-through. Figure 17 details the high off isolation rejection provided by this part. At 1MHz, off isolation is about 5dB in 5Ω systems, decreasing approximately db per decade as frequency increases. Higher load impedances decrease off isolation rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and or. FN7876 Rev. Page 8 of 12

9 Typical Performance urves T A =, Unless Otherwise Specified. r ON (Ω) (V) FIGURE 9. ON-RESISTANE vs SUPPLY VOLTAGE r ON (Ω) = 3.3V = 5V = 12V V OM (V) FIGURE 1. ON-RESISTANE vs SWITH VOLTAGE r ON (Ω) V OM (V) FIGURE 11. r ON MATH vs SWITH VOLTAGE = 3.3V = 5V = 12V Q (p) 6 5 = 5V = 12V 1 = 3.3V V OM (V) FIGURE 12. HARGE INJETION vs SWITH VOLTAGE t ON (ns) (V) FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE t OFF (ns) (V) FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE FN7876 Rev. Page 9 of 12

10 Typical Performance urves T A =, Unless Otherwise Specified. (ontinued) V INH AND V INL (V) V INH V INL (V) FIGURE 15. DIGITAL SWITHING POINT vs SUPPLY VOLTAGE NORMALIZED GAIN (db) -3-6 = 3.3V TO 12V GAIN PHASE R L = 5Ω V IN =.2V P-P TO 2.5V P-P ( = 3.3V) V IN =.2V P-P TO 4V P-P ( = 5V) V IN =.2V P-P TO 5V P-P ( = 12V) FREQUENY (MHz) FIGURE 16. FREQUENY RESPONSE PHASE ( ) 1 = 3V TO 13V R L = 5Ω OFF ISOLATION (db) ISOLATION ±PSRR (db) = 3.3V, SWITH OFF = 12V, SWITH OFF = 12V, SWITH ON = 3.3V, SWITH ON k 1k 1k 1M 1M 1M 5M FREQUENY (Hz) FIGURE 17. OFF ISOLATION Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: ISL4321A: 58 PROESS: Si Gate MOS FREQUENY (MHz) FIGURE 18. ±PSRR vs FREQUENY FN7876 Rev. Page 1 of 12

11 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION HANGE June 24, 11 FN7876. Initial release Products Intersil orporation is a leader in the design and manufacture of high-performance analog semiconductors. The ompany's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL4321A To report errors or suggestions for this datasheet, please go to: FITs are available from our website at: opyright Intersil Americas LL 11. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN7876 Rev. Page 11 of 12

12 Package Outline Drawing P LEAD SMALL OUTLINE TRANSISTOR PLASTI PAKAGE Rev 4, 2/ A.95 D /-.1 3 PIN 1 INDEX AREA x (.6) B TOP VIEW. ±.1 3. M A-B D SEE DETAIL X END VIEW 2.9 ± TYP (2 PLS) / MAX (.25) GAUGE PLANE.1 SEATING PLANE SIDE VIEW.-.15 DETAIL "X".45±.1 4 (.95) (.6) (1.) NOTES: (2.) Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5M Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to gauge plane. Package conforms to JEDE MO-178AB. TYPIAL REOMMENDED LAND PATTERN FN7876 Rev. Page 12 of 12