DATASHEET ISL43L841. Features. Applications. Related Literature

Transcription

1 DATASHEET ISL43L841 Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer FN6212 Rev 1. The Intersil ISL43L841 device contains precision, bidirectional, analog switches configured as a differential 4-channel multiplexer/demultiplexer. It is designed to operate from a single +1.65V to +4.5V supply. The device has an inhibit pin to simultaneously open all signal paths. With a supply voltage of 4.2V and logic high voltage of 2.85V at the logic inputs, the part draws only 2µA max of I current. ON resistance is.47 with a +4.3V supply and.65 with a single +1.8V supply. Each switch can handle rail to rail analog signals. A channel can handle 3mA of continuous current. The part has low quiescent power consumption of.23µw max. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL43L841 is a differential 4 to 1 multiplexer device that is offered in a 16 Ld 3x3 TQFN package. Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANE ONFIGURATION Diff 4:1 Mux 4.3V R ON V t ON /t OFF 22ns/12ns 3V R ON.52 3V t ON /t OFF 25ns/15ns 1.8V R ON V t ON /t OFF 4ns/17ns PAKAGES 16 Ld 3x3 TQFN Features Pb-Free Plus Anneal (RoHS ompliant) Pin ompatible Replacement for the MAX4782 and MAX4618 ON Resistance (R ON ) - = +4.3V = +3.V = +1.8V R ON Matching Between hannels R ON Flatness Across Signal Range Single Supply Operation V to +4.5V Low Power onsumption (PD) <.23µW Low I urrent when VinH is not at the Rail Fast Switching Action (V S = +3V) - t ON ns - t OFF ns Guaranteed Break-Before-Make High urrent Handling apacity (3mA ontinuous) Available in 16 Ld 3x3 TQFN 1.8V MOS-Logic ompatible (+3V Supply) Applications Battery Powered, Handheld, and Portable Equipment - ellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops Portable Test and Measurement Medical Equipment Audio and Video Switching Related Literature Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches FN6212 Rev 1. Page 1 of 12

2 Pinout (Note 1) ISL43L841 (3x3 TQFN) TOP VIEW A2 A B OMA 1 12 B1 A OMB A1 3 1 B 4 LOGI 9 B N.. ADD ADD1 NOTE: 1. Switches Shown for Logic Inputs. Truth Table ISL43L841 ADD ADD1 SWITH ON 1 X X NONE A, B 1 A1, B1 1 A2, B2 1 1 A3, B3 NOTE: Logic.5V. Logic 1 1.4V, with a 3V supply. X = Don t are. Pin Descriptions PIN FUNTION Ordering Information PART NO. ISL43L841IRZ (Note) ISL43L841IRZ-T (Note) PART MARKING L81Z L81Z TEMP. RANGE ( ) PAKAGE -4 to Ld 3x3 TQFN (Pb-Free) -4 to Ld 3x3 TQFN Tape and Reel (Pb-Free) PKG. DWG. # L16.3x3A L16.3x3A NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-2. System Power Supply Input (1.65V to 4.5V) N.. OMA OMB A-A3 B-B3 ADDx N onnect. Not internally connected. Ground onnection Inhibit Input Pin. onnect to for Normal Operation. onnect to to turn all switches off. Analog Switch hannel A Output Analog Switch hannel B Output Analog Switch hannel A Input Analog Switch hannel B Input Address Input Pin FN6212 Rev 1. Page 2 of 12

3 Absolute Maximum Ratings to to 4.7V Input Voltages, Ax, Bx, ADDx (Note 2) to () +.3V Output Voltages OMx (Note 2) to () +.3V ontinuous urrent NO or OM mA Peak urrent NO or OM (Pulsed 1ms, 1% Duty ycle, Max) mA ESD Rating HBM >4kV Thermal Information Thermal Resistance (Typical, Note 3) JA ( /W) 16 Ld 3x3 TQFN Package Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to 15 Maximum Lead Temperature (Soldering 1s) (Lead Tips Only) Operating onditions Temperature Range to 85 AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on Ax, Bx, OMx, ADDx, or exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB379. Electrical Specifications - 4.3V Supply Test onditions: V SUPPLY = +3.9V to +4.5V, = V, V = 1.4V, V INL =.4V (Notes 4, 8), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON = 3.9V, I OM = 1mA, V AX or V BX = V to, (See Figure 5) Full R ON Matching Between hannels, R ON R ON Flatness, R FLAT(ON) = 3.9V, I OM = 1mA, V AX or V BX = Voltage at max R ON, (Note 6) = 3.9V, I OM = 1mA, V AX or V BX = V t, (Note 7) Full Full = +4.5V, V = V ADD = V or (Note 1) Ax or Bx OFF Leakage urrent, = 4.5V, V OM =.3V, 3V, V AX or V BX = 3V,.3V na I Ax(OFF) or I Bx(OFF) Full na OM ON Leakage urrent, = 4.5V, V OM = V AX or V BX =.3V, 3V na I OM(ON) Full na DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, Full A I ADDL DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF Address Transition Time, t TRANS Break-Before-Make Time, t BBM = 3.9V, V Ax or V Bx = 3.V, = 5, L = 35pF, = 3.9V, V Ax or V Bx = 3.V, = 5, L = 35pF, = 3.9V, V AX or V BX = 3.V, = 5, L = 35pF, = 4.5V, V AX or V BX = 3.V, = 5, L = 35pF, (See Figure 3, Note 1) ns Full ns ns Full ns ns Full ns ns Full ns FN6212 Rev 1. Page 3 of 12

4 Electrical Specifications - 4.3V Supply Test onditions: V SUPPLY = +3.9V to +4.5V, = V, V = 1.4V, V INL =.4V (Notes 4, 8), Unless Otherwise Specified (ontinued) PARAMETER TEST ONDITIONS Input OFF apacitance, OFF f = 1MHz, V AX or V BX = V OM = V, (See Figure 7) pf OM OFF apacitance, OFF f = 1MHz, V AX or V BX = V OM = V, (See Figure 7) pf OM ON apacitance, OM(ON) f = 1MHz, V AX or V BX = V OM = V, (See Figure 7) pf OFF Isolation = 5, L = 35pF, f = 1kHz, db rosstalk, Note 9 (See Figures 4 and 6) db Total Harmonic Distortion (THD) f = 2Hz to 2kHz,.5Vp-p, = % POWER SUPPLY HARATERISTIS Power Supply Range Full V Positive Supply urrent, I+ = 4.5V, V, V ADD = V or, Switch On or Off A Full A Positive Supply urrent, I+ = 4.2V, V ADDx = 2.85V A NOTES: 4. V IN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. R ON matching between channels is calculated by subtracting the channel with the highest max R ON value from the channel with lowest max R ON value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 1% tested at +25. Limits across the full temperature range are guaranteed by design and correlation. 9. Between any two switches. 1. Guaranteed but not tested. TEMP ( ) MIN TYP MAX UNITS Electrical Specifications - 3V Supply Test onditions: V SUPPLY = +2.7V to +3.3V, = V, V = 1.4V, V INL =.4V (Notes 4, 8) Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON = 2.7V, I OM = 1mA, V AX or V BX = V to, See Figure 5 Full R ON Matching Between hannels, = 2.7V, I OM = 1mA, V AX or V BX = Voltage at DR ON max R ON, (Note 6) Full R ON Flatness, R FLAT(ON) = 2.7V, I OM = 1mA, V AX or V BX = V t, (Note 7) Full DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, Full A I ADDL ADD DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF = 2.7V, V Ax or V Bx = 1.5V, = 5, L = 35pF, = 2.7V, V Ax or V Bx = 1.5V, = 5, L = 35pF, ns Full ns ns Full ns FN6212 Rev 1. Page 4 of 12

5 Electrical Specifications - 3V Supply Test onditions: V SUPPLY = +2.7V to +3.3V, = V, V = 1.4V, V INL =.4V (Notes 4, 8) Unless Otherwise Specified (ontinued) PARAMETER Address Transition Time, t TRANS TEST ONDITIONS = 2.7V, V AX or V BX = 1.5V, = 5, L = 35pF, ns Full ns Break-Before-Make Time, t BBM = 3.3V, V AX or V BX = 1.5V, = 5, L = 35pF, ns (See Figure 3, Note 1) Full ns harge Injection, Q L = 1.nF, V G = V, R G = W, (See Figure 2) p Input OFF apacitance, OFF f = 1MHz, V AX or V BX = V OM = V, (See Figure 7) pf OM OFF apacitance, OFF f = 1MHz, V AX or V BX = V OM = V, (See Figure 7) pf OM ON apacitance, OM(ON) f = 1MHz, V AX or V BX = V OM = V, (See Figure 7) pf OFF Isolation = 5, L = 35pF, f = 1kHz, db rosstalk, (Note 9) (See Figures 4 and 6) db Total Harmonic Distortion (THD) f = 2Hz to 2kHz,.5Vp-p, RL = % POWER SUPPLY HARATERISTIS Power Supply Range Full V Positive Supply urrent, I+ = 3.6V, V, V ADD = V or, Switch On or Off A Full A TEMP ( ) MIN TYP MAX UNITS Electrical Specifications - 1.8V Supply Test onditions: = +1.8V, = V, V = 1V, V INL =.4V (Notes 4, 8), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON Resistance, R ON = 1.8V, I OM = 1.mA, V AX or V BX = 1.V, (See Figure 5) Full R ON Matching Between hannels, = 1.8V, I OM = 1.mA, V AX or V BX = 1.V, R ON (See Figure 5) Full R ON Flatness, R FLAT(ON) = 1.8V, I OM = 1.mA, V AX or V BX = V,.9V, V, (See Figure 5) Full DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, Full A I ADDL ADD DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF Address Transition Time, t TRANS Break-Before-Make Time, t BBM = 1.8V, V Ax or V Bx = 1.V, = 5, L = 35pF, = 1.8V, V Ax or V Bx = 1.V, = 5, L = 35pF, = 1.8V, V AX or V BX = 1.V, = 5, L = 35pF, = 1.8V, V AX or V BX = 1.V, = 5, L = 35pF, (See Figure 3, Note 1) ns Full ns ns Full ns ns Full ns ns harge Injection, Q L = 1.nF, V G = V, R G = See Figure 2) p FN6212 Rev 1. Page 5 of 12

6 Test ircuits and Waveforms LOGI V 5% t ON t r < 5ns t f < 5ns A, B A1, A2, B1, OMA B2, A3, B3 OMB VA, VB SWITH OUTPUT V t OFF 9% 9% LOGI ADD-1 5 L 35pF Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. IBIT t ON /t OFF MEASUREMENT POINTS Repeat test for other switches. L includes fixture and stray capacitance. = V (NO or N) + R ON FIGURE 1B. IBIT t ON /t OFF TEST IRUIT LOGI V 5% t r < 5ns t f < 5ns t TRANS A, B SWITH OUTPUT VA, VB VA3, VB3 1% V 9% LOGI A1, A2, B1, OMA, B2, A3, B3 OMB ADD-1 5 L 35pF t TRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. L includes fixture and stray capacitance. = V (NO or N) + R ON FIGURE 1. ADDRESS t TRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS t TRANS TEST IRUIT FIGURE 1. SWITHING TIMES LOGI SWITH OUTPUT OFF ON OFF V V G R G HANNEL SELET Ax, Bx ADD1 ADD OMA, OMB LOGI L 1pF Q = x L Repeat test for other switches. FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2B. Q TEST IRUIT FIGURE 2. HARGE INJETION FN6212 Rev 1. Page 6 of 12

7 Test ircuits and Waveforms (ontinued) LOGI SWITH OUTPUT V V t BBM t r < 5ns t f < 5ns 9% LOGI A-A3 B-B3 ADD-1 OMA OMB 5 L 35pF FIGURE 3A. t BBM MEASUREMENT POINTS Repeat test for other switches. L includes fixture and stray capacitance. FIGURE 3B. t BBM TEST IRUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 1nF SIGNAL GENERATOR Ax or Bx R ON = V 1 /1mA Ax or Bx ANALYZER OMx ADD1 ADD V or HANNEL SELET V X 1mA V 1 OMA or OMB ADD1 ADD V or HANNEL SELET Off-Isolation is measured between OM and Off NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded. FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE 5. R ON TEST IRUIT V or SIGNAL GENERATOR A x OM A 5 Ax or Bx ANALYZER V or HANNEL SELET ADD1 ADD OM B B x N.. IMPEDANE ANALYZER ADD1 ADD OMA or OMB HANNEL SELET rosstalk is measured between adjacent channels with one channel ON and the other channel OFF. Signal direction through switch is reversed and worst case values are recorded. FIGURE 6. ROSSTALK TEST IRUIT FIGURE 7. APAITANE TEST IRUIT FN6212 Rev 1. Page 7 of 12

8 Detailed Description The ISL43L841 analog multiplexer offers precise switching capability from a single 1.65V to 4.5V supply with low onresistance (.47 ) and high speed operation (t ON = 24ns, t OFF = 14ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (1.65V), low power consumption (.23µW), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing and Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (see Figure 8). To prevent forward biasing these diodes, must be applied before any input signals, and the input signal voltages must remain between and. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pins and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the submicroamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low R ON switch. onnecting schottky diodes to the signal pins as shown in Figure 8 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current. OPTIONAL SHOTTKY DIODE OPTIONAL PROTETION RESISTOR OPTIONAL SHOTTKY DIODE ADD X V NOx V OM FIGURE 8. OVERVOLTAGE PROTETION Power-Supply onsiderations The ISL43L841 construction is typical of most MOS analog switches, in that they have two supply pins: and. and drive the internal MOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL43L V maximum supply voltage provides plenty of room for the 1% tolerance of 4.3V supply, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V but the part will operate with a supply below 1.65V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance urves for details. and power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switch and signals to drive the analog switch gate terminals. This device cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds These devices are 1.8V MOS compatible (.5V and 1.4V) over a supply range of 2.5V to 4.5V (see Figure 15). At 2.5V the V INL level is about.52v. This is still above the 1.8V MOS guaranteed minimum level of.4v, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. The ISL43L841 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (V to ). For example driving the device with 2.85V logic (V to 2.85V) while operating with a 4.2V supply, the device draws only 1µA of current when both address inputs are high (see Figure 13 for V LOGI = 2.85V). High-Frequency Performance In 5 systems, signal response is reasonably flat even past 1MHz with a -3dB bandwidth of 7MHz (see Figure 19). The frequency response is very consistent over a wide range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch s input to its output. Off Isolation is the resistance to this feed through, while rosstalk indicates the amount of feed through from one switch to another. Figure 2 details the high Off Isolation and rosstalk rejection provided by this family. At 1kHz, Off Isolation is about 65dB in 5 systems, decreasing approximately 2dB per decade as frequency increases. Higher load impedances decrease Off Isolation and rosstalk rejection FN6212 Rev 1. Page 8 of 12

9 due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and or. Typical Performance urves T A = 25, Unless Otherwise Specified.75.7 = 1.65V I OM = 1mA.6.55 = 4.3V I OM = 1mA R ON ( ) = 1.8V R ON ( ) = 2.7V.4 = 3V.45 = 3.6V = 4.3V V OM (V) FIGURE 9. ON RESISTANE vs SUPPLY VOLTAGE vs SWITH VOLTAGE V OM (V) FIGURE 1. ON RESISTANE vs SWITH VOLTAGE.65.6 = 3V I OM = 1mA.75.7 = 1.8V I OM = 1mA R ON ( ) R ON ( ) V OM (V) FIGURE 11. ON RESISTANE vs SWITH VOLTAGE V OM (V) FIGURE 12. ON RESISTANE vs SWITH VOLTAGE FN6212 Rev 1. Page 9 of 12

10 Typical Performance urves T A = 25, Unless Otherwise Specified (ontinued) 5 = 4.2V SWEEPING TWO LOGI S = 1.8V i (µa) 2 Q (p) SWEEPING ONE LOGI -8-9 = 3V V LOGI (V) V OM (V) FIGURE 13. I+ URRENT vs LOGI VOLTAGE FIGURE 14. HARGE INJETION vs SWITH VOLTAGE V AND V INL (V) V V INL t RANS (ns) (V) FIGURE 15. DIGITAL SWITHING POINT vs SUPPLY VOLTAGE (V) FIGURE 16. ADDRESS TRANS TIME vs SUPPLY VOLTAGE t ON (ns) t OFF (ns) (V) FIGURE 17. IBIT TURN - ON TIME vs SUPPLY VOLTAGE (V) FIGURE 18. IBIT TURN - OFF TIME vs SUPPLY VOLTAGE FN6212 Rev 1. Page 1 of 12

11 Typical Performance urves T A = 25, Unless Otherwise Specified (ontinued) NORMALIZED GAIN (db) = 3V GAIN -1 PHASE = 5 V IN =.2V P-P to 2V P-P.1M 1M 1M 1M FREQUENY (Hz) FIGURE 19. FREQUENY RESPONSE PHASE ( ) ROSSTALK (db) = 3V ISOLATION ROSSTALK k 1k 1k 1M 1M 1M 5M FREQUENY (Hz) FIGURE 2. ROSSTALK AND OFF ISOLATION OFF ISOLATION (db) Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): (QFN Paddle onnection: To Ground or Float) TRANSISTOR OUNT: 228 PROESS: Si Gate MOS opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN6212 Rev 1. Page 11 of 12

12 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) ) 6 INDEX AREA A 4X X.15 B 2X.15 A SEATING PLANE 4X P (DATUM B) (DATUM A) 6 INDEX AREA 4X P NX L 8 L 9 N N e D D1 D2 D2 2 D/2 D1/2 TOP VIEW SIDE VIEW NX b (Nd-1)Xe REF. N NX b E1/2 E/2 A.1 M A B SETION "-" e TERMINAL TIP FOR ODD TERMINAL/SIDE 5 BOTTOM VIEW 5 L1 7 L 1 2X.15 A A3 NX k A2 8 E2/2 A1 E2 A1 E E B 2X.15 B.8 (Ne-1)Xe REF. L / / 9 9 ORNER OPTION 4X.1 e L1 L 1 FOR EVEN TERMINAL/SIDE L16.3x3A 16 LEAD THIN QUAD FLAT NO-LEAD PLASTI PAKAGE MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A A A A3.2 REF 9 b , 8 D 3. BS - D BS 9 D , 8, 1 E 3. BS - E BS 9 E , 8, 1 e.5 BS - k L N 16 2 Nd 4 3 Ne 4 3 P Rev. 6/4 NOTES: 1. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between.15mm and.3mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PB Land Pattern Design efforts, see Intersil Technical Brief TB Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 1. ompliant to JEDE MO-22WEED-2 Issue, except for the E2 and D2 MAX dimension. FN6212 Rev 1. Page 12 of 12