DATASHEET. Features. Applications. Related Literature ISL84051, ISL84052, ISL84053

Transcription

1 DATASHEET ISL8451, ISL8452, ISL8453 Low Voltage, Single and Dual Supply, 8-to-1 Multiplexer, Dual 4-to-1 Multiplexer and a Triple SPDT Analog Switch FN647 Rev.1. The Intersil ISL8451, ISL8452, ISL8453 devices are precision, bidirectional, analog switches configured as a 8-hannel multiplexer/demultiplexer (ISL8451), a dual differential 4-hannel multiplexer/demultiplexer (ISL8452) and a triple single pole/double throw (SPDT) switch (ISL8453) designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. All devices have an inhibit pin to simultaneously open all signal paths. ON-resistance is 6Ω with a ±5V supply and 125Ω with a single +5V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 5nA at +85 with a ±5V supply. All digital inputs have.8v to 2.4V logic thresholds, ensuring TTL/MOS logic compatibility when using a single +3.3V and +5V supply or dual ±5V supplies. The ISL8451 is a 8-to-1 multiplexer device. The ISL8452 is a dual 4-to-1 multiplexer device. The ISL8453 is a committed triple SPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this family. ONFIGURATION TABLE 1. FEATURES AT A GLANE Related Literature ISL8451 ISL8452 ISL8453 8:1 Mux DUAL 4:1 Mux TRIPLE SPDT ±5V r ON 6Ω 6Ω 6Ω ±5V t ON /t OFF 5ns/4ns 5ns/4ns 5ns/4ns 5V r ON 125Ω 125Ω 125Ω 5V t ON /t OFF 9ns/6ns 9ns/6ns 9ns/6ns 3V r ON 25Ω 25Ω 25Ω 3V t ON /t OFF 18ns/ns 18ns/ns 18ns/ns Packages 16 Ld SOI 16 Ld SOI 16 Ld SOI 16 Ld QSOP 16 Ld QSOP 16 Ld QSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches Features Drop-in Replacements for MAX451/MAX451A, MAX452/MAX452A and MAX453/MAX453A Pin ompatible with MAX4581, MAX4582, MAX4583 and with Industry Standard 74H451, 74H452 and 74H453 ON-Resistance (r ON ) Max, V S = ±5V Ω ON-Resistance (r ON ) Max, V S = +5V Ω r ON Matching Between hannels <6Ω Low harge Injection p Single Supply Operation V to +12V Dual Supply Operation ±2V to ±6 Fast Switching Action (V S = +5V) - t ON ns - t OFF ns Guaranteed Max V S = ±5V nA Break-Before-Make TTL, MOS ompatible Pb-Free Available (RoHS ompliant) Applications Portable Equipment ommunications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems Test Equipment - Medical Ultrasound - Magnetic Resonance Image - T and PET Scanners (MRI) - ATE - Electrocardiograph Audio and Video Signal Routing Various ircuits - +3V/+5V DAs and ADs - Sample and Hold ircuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset ircuits FN647 Rev.1. Page 1 of 19

2 Pin onfigurations ISL8451 (16 LD SOI, QSOP, TSSOP) TOP VIEW ISL8452 (16 LD SOI, QSOP, TSSOP) TOP VIEW NO NOB 1 16 NO NO2 NO1B 2 15 NO1A OM 3 14 NO4 OMB 3 14 NO2A NO NO NO3B 4 13 OMA NO NO6 NO2B 5 12 NOA 6 LOGI 11 ADD 6 11 NO3A ADDB ADDA 7 8 LOGI 1 9 ADDB ADDA ISL8453 (16 LD SOI, QSOP, TSSOP) TOP VIEW NOB 1 16 NB 2 15 OMB NOA 3 14 OM OMA 4 13 NO NA 5 12 N 6 11 ADD 7 1 ADDB 8 9 ADDA NOTE: 1. Switches Shown for Logic Inputs. Pin Description PIN NUMBER PIN NAME ISL8451 ISL8452 ISL8453 FUNTION Positive Power Supply Input Negative Power Supply Input. onnect to for Single Supply onfigurations Ground onnection Digital ontrol Input. onnect to for Normal Operation. onnect to to turn all switches off. OM Analog Switch ommon Pin OMA OMB OM NO1, NO3, NO7, NO5, NO6, NO4, NO2 1, 2, 4, 5, 12, 14, Analog Switch Normally Open Pin FN647 Rev.1. Page 2 of 19

3 Pin Description (ontinued) PIN NUMBER PIN NAME ISL8451 ISL8452 ISL8453 FUNTION NOB, NO1B, NO3B, NO2B, NO3A, NOA, NO2A, NO1A - 1, 2, 4, 5, 11, 12, 14, 15 - Analog Switch Normally Open Pin NOB, NOA, NO - - 1, 3, 13 NB, NA, N - - 2, 5, 12 Analog Switch Normally losed Pin ADDA, ADDB, ADD 9, , 1-9, 1 11 Address Input Pin Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( ) PAKAGE (Pb-free) PKG. DWG. # ISL8451IAZ 8451 IAZ -4 to Ld QSOP M16.15A ISL8451IBZ 8451IBZ -4 to Ld SOI M16.15 ISL8451IVZ 8451 IVZ -4 to Ld TSSOP M ISL8452IAZ 8452 IAZ -4 to Ld QSOP M16.15A ISL8452IBZ 8452IBZ -4 to Ld SOI M16.15 ISL8452IVZ 8452 IVZ -4 to Ld TSSOP M ISL8453IAZ 8453 IAZ -4 to Ld QSOP M16.15A ISL8453IBZ 8453IBZ -4 to Ld SOI M16.15 ISL8453IVZ 8453 IVZ -4 to Ld TSSOP M NOTES: 2. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-2 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL8451, ISL8452, ISL8453. For more information on MSL please see techbrief TB363. FN647 Rev.1. Page 3 of 19

4 Truth Tables ISL8451 ADD ADDB ADDA SWITH ON 1 X X X None NO 1 NO1 1 NO2 ISL8452 ADDB ADDA SWITH ON 1 X X None NO 1 NO1 1 NO2 1 1 NO3 1 1 NO3 1 NO4 1 1 NO5 1 1 NO NO7 ISL8453 ADD ADD B ADD A SWITH ON 1 X X X None X X N A X X 1 NO A X X N B X 1 X NO B X X N 1 X X NO NOTE: Logic.8V. Logic 1 2.4V, with between 2.7V and 1V. X = Don t are. FN647 Rev.1. Page 4 of 19

5 Absolute Maximum Ratings to V to 15V to V to 15V to V to.3v Input Voltages, NO, N, ADD (Note 5) (() -.3) to (() +.3V) Output Voltages OM (Note 5) (() -.3) to (() +.3V) ontinuous urrent (Any Terminal) ±3mA Peak urrent NO, N, or OM (Pulsed 1ms, 1% Duty ycle, Max) ±ma ESD Rating Human Body Model (Per MIL-STD-883, Method 315.7) >2kV Thermal Information Thermal Resistance (Typical, Notes 6, 7) JA ( /W) J ( /W) 16 Ld SOI Package Ld QSOP Package Ld TSSOP Package Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +15 Pb-Free Reflow Profile see link below Operating onditions Temperature Range to +85 AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Signals on N, NO, OM, ADD, or exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For J, the case temp location is taken at the package top center. Electrical Specifications 5V Supply Test onditions: V SUPPLY = ±4.5V to ±5.5V, = V, V = 2.4V, V INL =.8V (Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON V S = ±5V, I OM = 1mA, V NO or V N = ±3V (see Figure 5) Ω Full Ω r ON Matching Between hannels, V S = ±5V, I OM = 1mA, V NO or V N = ±3V (Note 11) Ω r ON Full Ω r ON Flatness, r FLAT(ON) NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OM OFF Leakage urrent, I OM(OFF), (ISL8451) OM OFF Leakage urrent, I OM(OFF), (ISL8452, ISL8453) OM ON Leakage urrent, I OM(ON), (ISL8451) V S = ±5V, I OM = 1mA, V NO or V N = ±3V, V (Note 12) V S = ±5.5V, V OM = ±4.5V, V NO or V N = ±4.5V (Note 12) V S = ±5.5V, V OM = ±4.5V, V NO or V N = ±4.5V (Note 12) V S = ±5.5V, V OM = ±4.5V, V NO or V N = ±4.5V (Note 12) V S = ±5.5V, V OM = V NO or V N = ±4.5V (Note 12) Ω Full Ω na Full -5-5 na na Full -5-5 na na Full na na Full -5-5 na OM ON Leakage urrent, I OM(ON), (ISL8452, ISL8453) DIGITAL HARATERISTIS V S = ±5.5V, V OM = V NO or V N = ±4.5V (Note 12) na Full na Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, I ADDL V S = ±5.5V, V, V ADD = V or Full µa FN647 Rev.1. Page 5 of 19

6 Electrical Specifications 5V Supply Test onditions: V SUPPLY = ±4.5V to ±5.5V, = V, V = 2.4V, V INL =.8V (Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF Address Transition Time, t TRANS Break-Before-Make Time, t BBM V S = ±4.5V, V NO or V N = ±3V, = 3Ω, L = 35pF, V IN = V to 3V (see Figure 1) V S = ±4.5V, V NO or V N = ±3V, = 3Ω, L = 35pF, V IN = V to 3V (see Figure 1) V S = ±4.5V, V NO or V N = ±3V, = 3Ω, L = 35pF, V IN = V to 3V (see Figure 1) V S = ±5.5V, V NO or V N = 3V, = 3Ω, L = 35pF, V IN = V to 3V (see Figure 3) ns Full ns ns Full ns ns ns harge Injection, Q L = 1.nF, V G = V, R G = Ω (see Figure 2) p NO/N OFF-apacitance, OFF f = 1MHz, V NO or V N = V OM = V (see Figure 7) pf OM OFF-apacitance, OFF OM ON-apacitance, OM(ON) f = 1MHz, V NO or V N = V OM = V (see Figure 7) f = 1MHz, V NO or V N = V OM = V (see Figure 7) ISL pf ISL pf ISL pf ISL pf ISL pf ISL pf OFF Isolation rosstalk, (Note 9) (ISL8452, ISL8453 Only) POWER SUPPLY HARATERISTIS = 5Ω, L = 15pF, f = khz V NO or V N = 1V RMS (see Figures 4 and 6) <9 - db < -9 - db Power Supply Range Full ±2 - ±6 V Positive Supply urrent, I+ V S = ±5.5V, V, V ADD = V or, Switch On or Off µa Full -1-1 µa Negative Supply urrent, I µa Full -1-1 µa Electrical Specifications 5V Supply Test onditions: = +4.5V to +5.5V, = = V, V = 2.4V, V INL =.8V (Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON = 5V, I OM = 1.mA, V NO or V N = 3.5V (see Figure 5) Ω Full Ω NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OM OFF Leakage urrent, I OM(OFF), (ISL8451) OM OFF Leakage urrent, I OM(OFF), (ISL8452, ISL8453) = 5.5V, V OM = V, 4.5V, V NO or V N = 4.5V, V (Note 12) = 5.5V, V OM = V, 4.5V, V NO or V N = 4.5V, V (Note 12) = 5.5V, V OM = V, 4.5V, V NO or V N = 4.5V, V (Note 12) na Full -1-1 na na Full -1-1 na na Full -5-5 na FN647 Rev.1. Page 6 of 19

7 Electrical Specifications 5V Supply Test onditions: = +4.5V to +5.5V, = = V, V = 2.4V, V INL =.8V (Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS OM ON Leakage urrent, I OM(ON) = 5.5V, V OM = V NO or V N = 4.5V (Note 12) na Full -1-1 na DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, I ADDL = 5.5V, V, V ADD = V or Full µa DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF Break-Before-Make Time, t BBM = 4.5V, V NO or V N = 3V, = 3Ω, L =35pF, V IN = to 3V (see Figure 1) = 4.5V, V NO or V N = 3V, = 3Ω, L = 35pF, V IN = V to 3V (see Figure 1) = 5.5V, V NO or V N = 3V, = 3Ω, L = 35pF, V IN = V to 3V (see Figure 3) ns Full - - ns ns Full ns ns harge Injection, Q L = 1.nF, V G = V, R G = Ω (see Figure 2) p OFF Isolation rosstalk, (Note 9) (ISL8452, ISL84533 Only) POWER SUPPLY HARATERISTIS = 5Ω, L = 15pF, f = khz V NO or V N =1V RMS (see Figures 4 and 6) <9 - db <-9 - db Power Supply Range Full 2-12 V Positive Supply urrent, I+ = 5.5V, = V, V, V ADD = V or, Switch On or Off µa Full -1-1 µa Electrical Specifications 3.3V Supply Test onditions: = +3.V to +3.6V, = = V, V = 2.4V, V INL =.8V (Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON = 3V, I OM = 1.mA, V NO or V N = 1.5V Ω Full Ω NO or N OFF Leakage urrent, I NO(OFF) or I N(OFF) OM OFF Leakage urrent, I OM(OFF), (ISL8451) OM OFF Leakage urrent, I OM(OFF), (ISL8452, ISL8453) = 3.6V, V OM = V, 3V, V NO or V N = 3V, V (Note 12) = 3.6V, V OM = V, 3V, V NO or V N = 3V, V (Note 12) = 3.6V, V OM = V, 3V, V NO or V N = 3V, V (Note 12) na Full -1-1 na na Full -1-1 na na Full -5-5 na OM ON Leakage urrent, I OM(ON) = 3.6V, V OM = V NO or V N = 3V (Note 12) na Full -1-1 na DIGITAL HARATERISTIS Input Voltage High, V, V ADDH Full V FN647 Rev.1. Page 7 of 19

8 Electrical Specifications 3.3V Supply Test onditions: = +3.V to +3.6V, = = V, V = 2.4V, V INL =.8V (Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -4 to +85. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP MAX UNITS Input Voltage Low, V INL, V ADDL Full V Input urrent, I, I INL, I ADDH, I ADDL = 3.6V, V, V ADD = V or Full µa DYNAMI HARATERISTIS Inhibit Turn-ON Time, t ON Inhibit Turn-OFF Time, t OFF Break-Before-Make Time, t BBM = 3V, V NO or V N = 1.5V, = 3Ω, L = 35pF, V IN = V to 3V (see Figure 1) = 3V, V NO or V N = 1.5V, = 3Ω, L = 35pF, V IN = V to 3V (see Figure 1) = 3.6V, V NO or V N = 1.5V, = 3Ω, L =35pF, V IN = V to 3V (see Figure 3) ns Full ns ns Full ns ns harge Injection, Q L = 1.nF, V G = V, R G = Ω (see Figure 2) p OFF Isolation rosstalk, (Note 9) (ISL8452, ISL8453 Only) POWER SUPPLY HARATERISTIS = 5Ω, L = 15pF, f = khz V NO or V N = 1V RMS, (see Figures 4 and 6) <9 - db <-9 - db Power Supply Range Full 2-12 V Positive Supply urrent, I+ = 3.6V, = V, V, V ADD = V or Switch On or Off µa Full -1-1 µa NOTES: 8. V IN = Input voltage to perform proper function. 9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 1. ompliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11. r ON = r ON (MAX) - r ON (MIN). 12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 13. Between any two switches. FN647 Rev.1. Page 8 of 19

9 Test ircuits and Waveforms NO NO1-NO7 ISL8451 OM LOGI ADDA- 3Ω L 35pF LOGI 3V V 5% t ON t r < 2ns t f < 2ns NO NO1-NO3 ISL8452 OM SWITH OUTPUT V t OFF 9% 9% LOGI ADDA-B 3Ω L 35pF Logic input waveform is inverted for switches that have the opposite logic sense. N X NO X ISL8453 OM X LOGI ADD X 3Ω L 35pF Repeat test for other switches. L includes fixture and stray capacitance. = V (NO or N) + r ON FIGURE 1A. IBIT t ON /t OFF MEASUREMENT POINTS FIGURE 1. SWITHING TIMES FIGURE 1B. IBIT t ON /t OFF TEST IRUIT FN647 Rev.1. Page 9 of 19

10 Test ircuits and Waveforms (ontinued) NO NO7 NO1-NO6 ISL8451 OM LOGI ADDA- 3Ω L 35pF LOGI 3V V 5% t TRANS t r < 2ns t f < 2ns NO NO3 NO1-NO2 ISL8452 OM SWITH OUTPUT VNOX V 9% LOGI ADDA-B 3Ω L 35pF VNOX t TRANS 1% Logic input waveform is inverted for switches that have the opposite logic sense. N X NO X ISL8453 OM X LOGI ADD X 3Ω L 35pF Repeat test for other switches. L includes fixture and stray capacitance. = V (NO or N) + r ON FIGURE 1. ADDRESS t TRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS t TRANS TEST IRUIT FIGURE 1. SWITHING TIMES (ontinued) FN647 Rev.1. Page 1 of 19

11 Test ircuits and Waveforms (ontinued) LOGI SWITH OUTPUT OFF ON OFF D 3V V V G R G Ω NO or N ADDX OM LOGI L 1nF Q = D x L FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2. HARGE INJETION Repeat test for other switches. FIGURE 2B. Q TEST IRUIT NO-NO7 OM ADDA- 3Ω L 35pF LOGI ISL8451 LOGI 3V V t r < 2ns t f < 2ns NO-NO3 OM SWITH OUTPUT V t BBM 8% LOGI ADDA-B ISL8452 3Ω L 35pF NO X N X ISL8453 OM X L 3Ω 35pF ADD X LOGI FIGURE 3A. t BBM MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME Repeat test for other switches. L includes fixture and stray capacitance. FIGURE 3B. t BBM TEST IRUIT FN647 Rev.1. Page 11 of 19

12 Test ircuits and Waveforms (ontinued) SIGNAL GENERATOR NO or N r ON = V 1 /1mA NO or N V NX ADDX V OR 1mA V 1 ADDX V OR ANALYZER OM V OR OM FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE 5. r ON TEST IRUIT SIGNAL GENERATOR V OR NO A or N A OM A ISL8452 AND ISL8453 ADDX 5Ω IMPEDANE ANALYZER NO OR N ADDX V OR ANALYZER OM B NO B or N B N OM FIGURE 6. ROSSTALK TEST IRUIT Detailed Description The ISL8451, ISL8452, ISL8453 analog switches offer precise switching capability from a bipolar ±2V to ±6V or a single 2V to 12V supply with low on-resistance (6Ω) and high speed operation (t ON =5ns, t OFF = 4ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (3µW), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents FIGURE 7. APAITANE TEST IRUIT which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (see Figure 8). To prevent forward biasing these diodes, and must be applied before any input signals, and input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low r ON switch, so two small signal diodes can be FN647 Rev.1. Page 12 of 19

13 added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR FOOGI S 1kΩ LOGI V NO OR N Power-Supply onsiderations The ISL845x construction is typical of most MOS analog switches, in that they have three supply pins:,, and. and drive the internal MOS switches and set their analog voltage limits, so there are no connections between the analog signal path and. Unlike switches with a 13V maximum supply voltage, the ISL845x 15V maximum supply voltage provides plenty of room for the 1% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies. The minimum recommended supply voltage is 2V or ±2V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the Electrical Specification tables beginning on page 5 and Typical Performance urves beginning on page 14 for details. and power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched and signals to drive the analog switch gate terminals. OPTIONAL PROTETION DIODE V OM OPTIONAL PROTETION DIODE FIGURE 8. OVERVOLTAGE PROTETION Logic-Level Thresholds and power the internal logic stages, so has no affect on logic thresholds. This switch family is TTL compatible (.8V and 2.4V) over a supply range of 2.7V to 1V. At 12V the V IH level is about 3.5V. This is still below the MOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a V OH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. High-Frequency Performance In 5Ω systems, signal response is reasonably flat even past MHz (see Figure 17). Figure 17 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch s input to its output. Off isolation is the resistance to this feed through, while crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high off isolation and crosstalk rejection provided by this family. At 1MHz, off isolation is about 55dB in 5Ω systems, decreasing approximately 2dB per decade as frequency increases. Higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and. FN647 Rev.1. Page 13 of 19

14 Typical Performance urves T A = +25, Unless Otherwise Specified r ON (Ω) = -5V = V V OM = () - 1V I OM = 1mA (V) r ON (Ω) I OM = 1mA = 2.7V -4 = V = 3.3V = V 9 = 5V = V V OM (V) FIGURE 9. ON-RESISTANE vs SUPPLY VOLTAGE FIGURE 1. ON-RESISTANE vs SWITH VOLTAGE r ON (Ω) I OM = 1mA V S = ±2V V S = ±5V V OM (V) FIGURE 11. ON-RESISTANE vs SWITH VOLTAGE V S = ±3V Q (p) V S = ±5V V OM (V) = 5V = V FIGURE 12. HARGE INJETION vs SWITH VOLTAGE t ON (ns) = -5V V OM = () - 1V = V (V) FIGURE 13. IBIT TURN-ON TIME vs SUPPLY VOLTAGE t OFF (ns) = -5V = V (V) V OM = () - 1V FIGURE 14. IBIT TURN-OFF TIME vs SUPPLY VOLTAGE FN647 Rev.1. Page 14 of 19

15 Typical Performance urves T A = +25, Unless Otherwise Specified (ontinued) 3 25 V OM = () - 1V = V 25 2 V OM = () - 1V t RANS (ns) (V) FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE t RANS (ns) V± (V) FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE NORMALIZED GAIN (db) V S = ±5V 3 GAIN -3 PHASE = 5Ω V IN =.2V P-P TO 5V P-P ISL8453 ISL8451 ISL8452 ISL ISL8451 ISL M 1M M 6M FREQUENY (Hz) FIGURE 17. FREQUENY RESPONSE PHASE ( ) ROSSTALK (db) = 3V TO 12V or V S = ±2V TO ±5V = 5Ω ISOLATION ROSSTALK k 1k k 1M 1M M 5M FREQUENY (Hz) FIGURE 18. ROSSTALK AND OFF ISOLATION OFF ISOLATION (db) Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: ISL8451: 193 ISL8452: 193 ISL8453: 193 PROESS: Si Gate MOS FN647 Rev.1. Page 15 of 19

16 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION HANGE 5/2/11 FN onverted to new datasheet template. -Updated Intersil Trademark statement at bottom of page 1 per directive from Legal. -Added TSSOP Package option to ISL8453 in Pin onfiguration and ordering information. -Updated ordering information by removing withdrawn and obsolete non pb-free parts: ISL8451IA, ISL8451IA-T, ISL8451IB, ISL8451IB-T, ISL8452IA, ISL8451IB, ISL8453IA-T Updated notes in ordering information -Updated Parameters... note in Electrical Specifications tables to new ompliance... note according to standards -M onverted to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. -Added Revision History and Products Information. Products Intersil orporation is a leader in the design and manufacture of high-performance analog semiconductors. The ompany's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL8451, ISL8452, ISL8453 To report errors or suggestions for this datasheet, please go to: FITs are available from our website at: FN647 Rev.1. Page 16 of 19

17 Small Outline Plastic Packages (SOI) N INDEX AREA e D B.25(.1) M A M E -B- -A- -- SEATING PLANE A B S H.25(.1) M B A1.1(.4) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.14 inch) or greater above the seating plane, shall not exceed a maximum value of.61mm (.24 inch). 1. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. L M h x 45 M16.15 (JEDE MS-12-A ISSUE ) 16 LEAD NARROW BODY SMALL OUTLINE PLASTI PAKAGE ES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B D E e.5 BS 1.27 BS - H h L N Rev. 1 6/5 FN647 Rev.1. Page 17 of 19

18 Package Outline Drawing M LEAD THIN SHRINK SMALL OUTLINE PAKAGE (TSSOP) Rev 2, 5/1 A ± SEE DETAIL "X" ± PIN #1 I.D. MARK.2 B A B.9-.2 TOP VIEW END VIEW H REF SEATING PLANE.1 SIDE VIEW 1.2 MAX / M B A /-.1.5 MIN.15 MAX DETAIL "X" GAUGE PLANE -8.6 ± (1.45) NOTES: (5.65) (.65 TYP) (.35 TYP) TYPIAL REOMMENDED LAND PATTERN Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.15 per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed.25 per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y14.5M Dimension does not include dambar protrusion. Allowable protrusion shall be.8mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm. Dimension in ( ) are for reference only. onforms to JEDE MO-153. FN647 Rev.1. Page 18 of 19

19 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) N INDEX AREA e D B.17(.7) M A M E -B- -A- -- SEATING PLANE A B S H.25(.1) M B A1 NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be.1mm (.4 inch) total in excess of B dimension at maximum material condition. 1. ontrolling dimension: ES. onverted millimeter dimensions are not necessarily exact. GAUGE PLANE.1(.4).25.1 A2 M h x 45 L M16.15A 16 LEAD SHRINK SMALL OUTLINE PLASTI PAKAGE (.15 WIDE BODY) ES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B D E e.25 BS.635 BS - H h L N Rev. 2 6/4 opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN647 Rev.1. Page 19 of 19