DATASHEET ISL Features. Applications. Related Literature. Low-Voltage, Single and Dual Supply, 8-to-1 Multiplexer. FN6416 Rev 3.

Transcription

1 DATASHEET Low-Voltage, Single and Dual Supply, 8-to-1 Multiplexer The Intersil device contains precision, bidirectional, analog switches configured as an 8-to-1 multiplexer/demultiplexer. It was designed to operate from a single +2V to +12V single supply or from dual ±2V to ±6V supplies. The device has an inhibit pin to simultaneously open all signal paths. The has an ON-resistance of 39 with a dual ±5V supply and 125 with a single +3.3V supply. Each switch can handle rail-to-rail analog signals. The off-leakage current is only.2na at +25 or.2na at +85. All digital inputs have.8v to 2.4V logic thresholds, ensuring TTL/MOS logic compatibility when using a single 3.3V or +5V supply or dual ±5V supplies. The is a single 8-to-1 multiplexer device. Table 1 summarizes the performance of the part. TABLE 1. FEATURES AT A GLANE ONFIGURATION Related Literature SINGLE 8:1 MUX ±5V r ON 39 ±5V t ON /t OFF 32ns/18ns 12V r ON 32 12V t ON /t OFF 23ns/15ns 5V r ON 65 5V t ON /t OFF 38ns/19ns 3.3V r ON V t ON /t OFF 7ns/32ns Package 16 Ld TSSOP, 16 Ld QSOP Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches Application Note AN52 MOS Analog Multiplexers and Switches; Specifications and Application onsiderations. Application Note AN134 Analog Switch and Multiplexer Applications Features FN6416 Rev 3. Fully Specified at 3.3V, 5V, ±5V, and 12V Supplies for 1% Tolerances ON-Resistance (r ON ) Max, V S = ±4.5V ON-Resistance (r ON ) Max, V S = +3V r ON Matching Between hannels, V S = ±5V <2 Low harge Injection, V S = ±5V p (Max) Single Supply Operation V to +12V Dual Supply Operation V to 6V Fast Switching Action (V S = +5V) - t ON ns - t OFF ns Guaranteed Max Off-leakage nA Guaranteed Break-Before-Make TTL, MOS ompatible Pb-free (RoHS ompliant) Applications Battery Powered, Handheld, and Portable Equipment ommunications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems Test Equipment - Medical Ultrasound - Magnetic Resonance Image - T and PET Scanners (MRI) - ATE - Electrocardiograph Audio and Video Signal Routing Various ircuits - +3V/+5V DAs and ADs - Sample and Hold ircuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset ircuits FN6416 Rev 3. Page 1 of 15

2 Pinout (16 LD TSSOP, QSOP) TOP VIEW NO NO NO NO4 NO NO NO NO ADD 7 1 ADDB GND 8 9 ADDA NOTE: Switches Shown for Logic Inputs. Truth Tables ADD ADDB ADDA SWITH ON NO 1 NO1 1 NO2 1 1 NO3 1 NO4 1 1 NO5 1 1 NO NO7 Pin Descriptions PIN FUNTION Positive Power Supply Input Negative Power Supply Input. onnect to GND for Single Supply onfigurations. GND Ground onnection Digital ontrol Input. onnect to GND for Normal Operation. onnect to to turn all switches off. ADDx Address Input Pin Analog Switch ommon Pin NOx Analog Switch Normally Open Pin 1 X X X NONE NOTE: Logic.8V. Logic 1 2.4V, with between 2.7V and 1V. X = Don t are. Ordering Information PART NUMBER (Note) PART MARKING RANGE PAKAGE (Pb-free) PKG. DWG. # IVZ IVZ -4 to Ld TSSOP (4.4mm) M IVZ-T* IVZ -4 to Ld TSSOP (4.4mm) Tape and Reel M IAZ IAZ -4 to Ld QSOP (4.4mm) M16.15A IAZ-T* IAZ -4 to Ld QSOP (4.4mm) Tape and Reel M16.15A * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-2. FN6416 Rev 3. Page 2 of 15

3 Absolute Maximum Ratings to V to 15V to GND V to 15V to GND V to.3v Input Voltages, NOx, ADDx (Note 1) to (() +.3V) Output Voltages (Note 1) to (() +.3V) ontinuous urrent (Any Terminal) ±3mA Peak urrent NOx, (Pulsed 1ms, 1% Duty ycle, Max) ±ma ESD Rating Human Body Model (Per Mil-STD-883, Method 315.7).. >2.5kV Thermal Information Thermal Resistance (Typical, Note 2) JA ( /W) 16 Ld TSSOP Package Ld QSOP Package Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +1 Pb-free Reflow Profile see link below Operating onditions Temperature Range to +85 AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. Signals on NOx,, ADDx, exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications ±5V Supply Test onditions: V SUPPLY = ±4.5V to ±5.5V, GND = V, V = 2.4V, V INL =.8V (Note 3), Unless Otherwise Specified. TYP ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG (Note 1) Full - V ON-Resistance, r ON V S = ±4.5V, I = 2mA, V NO = 3V (See Figure 5) Full r ON Matching Between hannels, r ON V S = ±4.5V, I = 2mA, V NO = 3V (Note 5) Full r ON Flatness, r FLAT(ON) V S = ±4.5V, I = 2mA, V NO = ±3V,.1V (Note 6) Full NO OFF Leakage urrent, I NO(OFF) V S = ±5.5V, V = 4.5V, V NO = +4.5V (Note 7) na OFF Leakage urrent, I (OFF) V S = ±5.5V, V = 4.5V, V NO = +4.5V (Note 7) na ON Leakage urrent, I (ON) V S = ±5.5V, V = V NO = ±4.5V (Note 7) na DIGITAL HARATERISTIS Input Voltage High, V H, V ADDH Full V Input Voltage Low, V L, V ADDL Full V Input urrent, I ADDH, I ADDL, I H, I L V S = ±5.5V, V, V ADD = V or, (Note 9) Full µa DYNAMI HARATERISTIS IBIT Turn-ON Time, t ON IBIT Turn-OFF Time, t OFF Address Transition Time, t TRANS V S = ±4.5V, V NO = ±3V, R L = 3, L = 35pF, V IN = to 3 (See Figure 1, Note 9) V S = ±4.5V, V NO = ±3V, R L = 3, L = 35pF, V IN = to 3 (See Figure 1, Note 9) V S = ±4.5V, V NO = ±3V, R L = 3, L = 35pF, V IN = to 3 (See Figure 1, Note 9) ns Full - - ns ns Full ns ns Full ns FN6416 Rev 3. Page 3 of 15

4 Electrical Specifications ±5V Supply Test onditions: V SUPPLY = ±4.5V to ±5.5V, GND = V, V = 2.4V, V INL =.8V (Note 3), Unless Otherwise Specified. (ontinued) TYP Break-Before-Make Time, t BBM V S = ±5.5V, V NO = 3V, R L = 3, L = 35pF, V IN = to 3V (See Figure 3, Note 9) Full ns harge Injection, Q L = 1.nF, V G = V, R G = (See Figure 2, Note 9) p NO OFF apacitance, OFF f = 1MHz, V NO = V = V (See Figure 6) pf OFF apacitance, OFF f = 1MHz, V NO = V = V (See Figure 6) pf ON apacitance, (ON) f = 1MHz, V NO = V = V (See Figure 6) pf OFF-Isolation POWER SUPPLY HARATERISTIS R L =, L = 15pF, f = khz, V NOx = 1V RMS (See Figures 4 and 18) db Power Supply Range (Note 1) Full ±2 - ±6 V Positive Supply urrent, I+ V S = ±5.5V, V, V ADD = V or, Switch On or Full -7-7 µa Negative Supply urrent, I- Off, (Note 9) Full -1-1 µa Electrical Specifications +12V Supply Test onditions: = +1.8V to +13.2V, GND = V, V = 4V, V INL =.8V (Note 3), Unless Otherwise Specified. TYP ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG (Note 1) Full - V ON-Resistance, r ON = 1.8V, I = 1.mA, V NO = 9V (See Figure 5) Full r ON Matching Between hannels, = 1.8V, I = 1.mA, V NO = 9V (Note 5) r ON Full r ON Flatness, r FLAT(ON) = 1.8V, I = 1.mA, V NO = 3V, 6V, 9V (Note 6) Full NO OFF Leakage urrent, I NO(OFF) = 13.2V, V = 1V, 12V, V NO = 12V, 1V (Note 7) na OFF Leakage urrent, = 13.2V, V = 12V, 1V, V NO = 1V, 12V (Note 7) na I (OFF) ON Leakage urrent, I (ON) = 13.2V, V = 1V, 12V, V NO = 1V, 12V, or floating (Note 7) na DIGITAL HARATERISTIS Input Voltage High, V H, V ADDH Full V Input Voltage Low, V L, V ADDL Full V Input urrent, I ADDH, I ADDL, I H, = 13.2V, V, V ADD = V or Full µa I L DYNAMI HARATERISTIS IBIT Turn-ON Time, t ON IBIT Turn-OFF Time, t OFF = 1.8V, V NO = 1V, R L = 3, L = 35pF, V IN = to 4 (See Figure 1, Note 9) = 1.8V, V NO = 1V, R L = 3, L = 35pF, V IN = to 4 (See Figure 1, Note 9) ns Full ns ns Full ns FN6416 Rev 3. Page 4 of 15

5 Electrical Specifications +12V Supply Test onditions: = +1.8V to +13.2V, GND = V, V = 4V, V INL =.8V (Note 3), Unless Otherwise Specified. (ontinued) TYP Address Transition Time, t TRANS = 1.8V, V NO = 1V, R L = 3, L = 35pF, V IN = to 4 (See Figure 1, Note 9) ns Full ns Break-Before-Make Time Delay, t D = 13.2V, R L = 3, L = 35pF, V NO = 1V, V IN = to 4 (See Figure 3, Note 9) Full ns harge Injection, Q L = 1.nF, V G = V, R G = (See Figure 2, Note 9) p OFF-Isolation R L =, L = 15pF, f = khz (See Figures 4 and 18) db NO OFF apacitance, OFF f = 1MHz, V NO = V = V (See Figure 6) pf OFF apacitance, (OFF) f = 1MHz, V NO = V = V (See Figure 6) pf ON apacitance, (ON) f = 1MHz, V NO = V = V (See Figure 6) pf POWER SUPPLY HARATERISTIS Power Supply Range (Note 1) Full 2-12 V Positive Supply urrent, I+ = 13.2V, V, V ADD = V or, all channels on or off Full -7-7 µa Electrical Specifications 5V Supply Test onditions: = +4.5V to +5.5V, = GND = V, V = 2.4V, V INL =.8V (Note 3), Unless Otherwise Specified. TYP ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG (Note 1) Full - V ON-Resistance, r ON = 4.5V, I = 1.mA, V NO = 3.5V (See Figure 5) Full r ON Matching Between hannels, r ON = 4.5V, I = 1.mA, V NO = 3V (Note 5) Full r ON Flatness, r FLAT(ON) NO OFF Leakage urrent, I NO(OFF) OFF Leakage urrent, I (OFF) = 4.5V, I = 1.mA, V NO = 1V, 2V, 3V (Note 6) = 5.5V, V = 1V, 4.5V, V NO = 4.5V, 1V (Note 7) = 5.5V, V = 1V, 4.5V, V NO = 4.5V, 1V (Note 7) Full na na ON Leakage urrent, I (ON) = 5.5V, V = V NO = 4.5V (Note 7) na DIGITAL HARATERISTIS Input Voltage High, V H, V ADDH Full V Input Voltage Low, V L, V ADDL Full V Input urrent, I ADDH, I ADDL, I H, = 5.5V, V, V ADD = V or, (Note 9) Full µa I L DYNAMI HARATERISTIS IBIT Turn-ON Time, t ON = 4.5V, V NO = 3V, R L = 3, L = 35pF, V IN = to 3V (see Figure 1, Note 9) ns Full ns FN6416 Rev 3. Page 5 of 15

6 Electrical Specifications 5V Supply Test onditions: = +4.5V to +5.5V, = GND = V, V = 2.4V, V INL =.8V (Note 3), Unless Otherwise Specified. (ontinued) TYP IBIT Turn-OFF Time, t OFF Address Transition Time, t TRANS Break-Before-Make Time, t BBM = 4.5V, V NO = 3V, R L = 3, L = 35pF, V IN = to 3V (see Figure 1, Note 9) = 4.5V, V NO = 3V, R L = 3, L = 35pF, V IN = to 3V (see Figure 1, Note 9) = 5.5V, V NO = 3V, R L = 3, L = 35pF, V IN = to 3V (see Figure 3, Note 9) ns Full ns ns Full ns Full ns harge Injection, Q L = 1.nF, V G = V, R G = see Figure 2, Note 9) p OFF-Isolation POWER SUPPLY HARATERISTIS R L =, L = 15pF, f = khz, V NOx = 1V RMS (see Figures 4 and 18) db Power Supply Range (Note 1) Full 2-12 V Positive Supply urrent, I+ = 5.5V, = V, V, V ADD = V or, Full -7-7 µa Positive Supply urrent, I- Switch On or Off, (Note 9) Full -1-1 µa Electrical Specifications 3.3V SupplyTest onditions: = +3.V to +3.6V, = GND = V, V = 2.4V, V INL =.8V (Note 3), Unless Otherwise Specified TYP ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - V ON-Resistance, r ON = 3.V, I = 1.mA, V NO = 1.5V (see Figure 5) Full r ON Matching Between hannels, = 3.V, I = 1.mA, V NO = 1.5V (Note 5) r ON Full r ON Flatness, r FLAT(ON) = 3.V, I = 1.mA, V NO =.5V, 1V, 2V (Note 6) Full NO OFF Leakage urrent, I NO(OFF) = 3.6V, V = V, 4.5V, V NO = 3V, 1V (Note 7) na OFF Leakage urrent, = 3.6V, V = V, 4.5V, V NO = 3V, 1V (Note 7) na I (OFF) ON Leakage urrent, I (ON) = 3.6V, V = V NO = 3V (Note 7) na DIGITAL HARATERISTIS Input Voltage High, V H, V ADDH Full V Input Voltage Low, V L, V ADDL Full V Input urrent, I ADDH, I ADDL, I H, = 3.6V, V, V ADD = V or, (Note 9) Full A I L DYNAMI HARATERISTIS IBIT Turn-ON Time, t ON = 3.V, V NO = 1.5V, R L = 3, L = 35pF, V IN = V to 3V (see Figure 1, Note 9) ns Full ns FN6416 Rev 3. Page 6 of 15

7 Electrical Specifications 3.3V SupplyTest onditions: = +3.V to +3.6V, = GND = V, V = 2.4V, V INL =.8V (Note 3), Unless Otherwise Specified (ontinued) TYP IBIT Turn-OFF Time, t OFF Address Transition Time, t TRANS Break-Before-Make Time, t BBM = 3.V, V NO = 1.5V, R L = 3, L = 35pF, V IN = V to 3V (see Figure 1, Note 9) = 3.V, V NO = 1.5V, R L = 3, L = 35pF, V IN = V to 3V (see Figure 1, Note 9) = 3.6V, V NO = 1.5V, R L = 3, L = 35pF, V IN = V to 3V (see Figure 3, Note 9) ns Full - - ns ns Full ns Full ns harge Injection, Q L = 1.nF, V G = V, R G = see Figure 2, Note 9) p OFF-Isolation R L =, L = 15pF, f = khz, V NO = 1V RMS (see Figures 4 and 18) db POWER SUPPLY HARATERISTIS Power Supply Range (Note 1) Full 2-12 V NOTES: 3. V IN = Input logic voltage to configure the device in a given state. 4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. r ON = r ON () - r ON (). 6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 7. Leakage parameter is % tested at high temp, and guaranteed by correlation at Parameters with and/or limits are % tested at +25, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. Limits established by characterization and are not production tested. 1. Limits should be considered typical and are not production tested. Test ircuits and Waveforms 3V V % t ON t r < 2ns t f < 2ns NO NO1-NO7 V OUT SWITH OUTPUT VNO V t OFF 9% V OUT 9% GND ADDA- R L 3 L 35pF Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. IBIT t ON /t OFF MEASUREMENT POINTS Repeat test for other switches. L includes fixture and stray capacitance. R L V OUT = V (NO or N) R L + r ON FIGURE 1B. IBIT t ON /t OFF TEST IRUIT FN6416 Rev 3. Page 7 of 15

8 Test ircuits and Waveforms (ontinued) SWITH OUTPUT 3V V VNO V VNO X % t TRANS 1% V OUT t r < 2ns t f < 2ns 9% NO NO7 NO1-NO6 ADDA- GND V OUT R L 3 L 35pF t TRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. L includes fixture and stray capacitance. R L V OUT = V (NO or N) R L + r ON FIGURE 1. ADDRESS t TRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS t TRANS TEST IRUIT FIGURE 1. SWITHING TIMES SWITH OUTPUT V OUT OFF ON OFF V OUT 3V V V G R G NO ADDX GND L 1nF V OUT Q = V OUT x L Repeat test for other switches. FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2B. Q TEST IRUIT FIGURE 2. HARGE INJETION 3V V t r < 2ns t f < 2ns V OUT NO-NO7 R L 3 L 35pF SWITH OUTPUT V OUT V t BBM 8% ADDA- GND FIGURE 3A. t BBM MEASUREMENT POINTS Repeat test for other switches. L includes fixture and stray capacitance. FIGURE 3B. t BBM TEST IRUIT FIGURE 3. BREAK-BEFORE-MAKE TIME FN6416 Rev 3. Page 8 of 15

9 Test ircuits and Waveforms (ontinued) SIGNAL GENERATOR NOx r ON = V 1 /1mA NO V NOX ADDX V OR 1mA V 1 ADDX V OR ANALYZER GND V OR GND R L FIGURE 4. OFF-ISOLATION TEST IRUIT FIGURE 5. r ON TEST IRUIT NOx IMPEDANE ANALYZER ADDX V OR GND FIGURE 6. APAITANE TEST IRUIT FN6416 Rev 3. Page 9 of 15

10 Detailed Description The multiplexer offers precise switching capability from bipolar ±2V to ±6V supplies or a single 2V to 12V supply. When powered with dual ±5V supplies the part has low ON-resistance (39 ) and high speed operation (t ON = 38ns, t OFF = 19ns). It has an inhibit pin to simultaneously open all signal paths. The device is especially well suited for applications using ±5V supplies. With ±5V supplies the performance (r ON, Leakage, harge Injection, etc.) is best in class. High frequency applications also benefit from the wide bandwidth and high off-isolation. Supply Sequencing And Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (see Figure 7). To prevent forward biasing these diodes, and must be applied before any input signals, and input signal voltages must remain between and. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low r ON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 7). These additional diodes limit the analog signal from 1V below to 1V above. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTETION RESISTOR FOR S 1k V NOx OPTIONAL PROTETION DIODE V Power-Supply onsiderations The construction is typical of most MOS analog switches, in that it has three supply pins:,, and GND. and drive the internal MOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the 15V maximum supply voltage provides plenty of room for the 1% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. The part performs equally well when operated with bipolar or single voltage supplies.the minimum recommended supply voltage is 2V single supply or ±2V dual supply. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the Electrical Specification tables on page 4 and Typical Performance urves on page 11 for details. and GND power the internal logic setting the digital switching point of the level shifters. The level shifters convert the logic levels to switched and signals to drive the analog switch gate terminals. Logic-Level Thresholds and GND power the internal logic stages, so has no affect on logic thresholds. This is TTL compatible (.8V and 2.4V) over a supply range of 2.7V to 1V. At 12V the V IH level is about 3.3V. This is still below the MOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a V OH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to with a fast transition time minimizes power dissipation. High-Frequency Performance In systems, signal response is reasonably flat even past MHz (see Figures 16 and 17). Figures 16 and 17 also illustrate that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch s input to its output. Off-isolation is the resistance to this feed through. Figure 18 details the high off isolation of the. At 1MHz, off-isolation is about 55dB in systems, decreasing approximately 2dB per decade as frequency increases. Higher load impedances decrease off-isolation due to the voltage divider action of the switch OFF impedance and the load impedance. OPTIONAL PROTETION DIODE FIGURE 7. OVERVOLTAGE PROTETION FN6416 Rev 3. Page 1 of 15

11 Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. Typical Performance urves T A = +25, Unless Otherwise Specified r ON ( ) = -5V = V V = () - 1V I = 1mA (V) FIGURE 8. ON-RESISTANE vs SUPPLY VOLTAGE r ON ( ) I = 1mA V S = ±5V V S = ±2V V S = ±3V V (V) FIGURE 9. ON-RESISTANE vs SWITH VOLTAGE r ON ( ) I = 1mA = 2.7V -4 = V = 3.3V 8-4 = V 9 = 5V = V V (V) FIGURE 1. ON-RESISTANE vs SWITH VOLTAGE r ON ( ) = 12V I = 1mA 55 = V V (V) FIGURE 11. ON-RESISTANE vs SWITH VOLTAGE FN6416 Rev 3. Page 11 of 15

12 Typical Performance urves T A = +25, Unless Otherwise Specified (ontinued) t ON (ns) = -5V V = () - 1V = V (V) FIGURE 12. IBIT TURN-ON TIME vs SUPPLY VOLTAGE t OFF (ns) = -5V = V V = () - 1V (V) FIGURE 13. IBIT TURN-OFF TIME vs SUPPLY VOLTAGE 3 2 V = () - 1V = V 2 2 V = () - 1V t RANS (ns) (V) FIGURE 14. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE t RANS (ns) V± (V) +85 FIGURE 15. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE NORMALIZED GAIN (db) 3-3 V S = ±5V GAIN PHASE V IN =.2V P-P TO 5V P-P 45 NORMALIZED GAIN (db) 3-3 V S = ±3V GAIN PHASE V IN =.2V P-P TO 4V P-P 45 R L = 1M 1M M M FREQUENY (Hz) FIGURE 16. FREQUENY RESPONSE PHASE ( ) R L = 1M 1M M M FREQUENY (Hz) FIGURE 17. FREQUENY RESPONSE PHASE ( ) FN6416 Rev 3. Page 12 of 15

13 Typical Performance urves T A = +25, Unless Otherwise Specified (ontinued) OFF ISOLATION (db) = 3V TO 12V OR V S = ±2V TO ±5V R L = ISOLATION Q (p) = 3.3V = V V S = ±5V = 5V = V = 12V = V k 1k k 1M 1M M M FREQUENY (Hz) FIGURE 18. OFF ISOLATION V (V) FIGURE 19. HARGE INJETION vs SWITH VOLTAGE Die haracteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: 193 PROESS: Si Gate MOS FN6416 Rev 3. Page 13 of 15

14 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) N INDEX AREA e D B.17(.7) M A M E -B- -A- -- SEATING PLANE A B S H.25(.1) M B A1 NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be.1mm (.4 inch) total in excess of B dimension at maximum material condition. 1. ontrolling dimension: INHES. onverted millimeter dimensions are not necessarily exact. GAUGE PLANE.1(.4).25.1 A2 M h x 45 L M16.15A 16 LEAD SHRINK SMALL OUTLINE PLASTI PAKAGE (.1 WIDE BODY) INHES MILLIMETERS SYMBOL NOTES A A A B D E e.25 BS.635 BS - H h L N Rev. 2 6/4 FN6416 Rev 3. Page 14 of 15

15 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA (.2) e D.1(.4) M A M E1 -B- -Ab -- SEATING PLANE A B S E.25(.1) M B A1 NOTES: 1. These package dimensions are within allowable dimensions of JEDE MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.15mm (.6 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch). 1. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. (Angles in degrees) GAUGE PLANE.1(.4).25.1 A2 M L c M LEAD THIN SHRINK SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL NOTES A A A b c D E e.26 BS.65 BS - E L N o 8 o o 8 o - Rev. 1 2/2 opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN6416 Rev 3. Page 15 of 15