DATASHEET HIP4081A. Features. Applications. Ordering Information. Pinout. 80V/2.5A Peak, High Frequency Full Bridge FET Driver

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1 DATASHEET HIP408A 80V/.5A Peak, High Frequency Full Bridge FET Driver FN659 Rev 8.00 The HIP408A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 0 lead plastic SOIC and DIP packages. The HIP408A can drive every possible switch combination except those which would cause a shoot-through condition. The HIP408A can switch at frequencies up to MHz and is well suited to driving Voice Coil Motors, high-frequency switching power amplifiers, and power supplies. For example, the HIP408A can drive medium voltage brush motors, and two HIP408As can be used to drive high performance stepper motors, since the short minimum on-time can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load. A similar part, the HIP4080A, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate hysteresis mode switching. The Application Note for the HIP408A is the AN9405. Ordering Information PART NUMBER HIP408AIP (No longer available, recommended replacement: HIP408AIPZ) HIP408AIPZ (Note) TEMP RANGE ( C) PACKAGE PKG. DWG. # -40 to 85 0 Ld PDIP E to 85 0 Ld PDIP (Pb-free) E0. HIP408AIB -40 to 85 0 Ld SOIC (W) M0. HIP408AIBZ (Note) -40 to 85 0 Ld SOIC (W) M0. (Pb-free) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-00B. Features Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations Bootstrap Supply Max Voltage to 95V DC Drives 000pF Load at MHz in Free Air at C with Rise and Fall Times of Typically 0ns User-Programmable Dead Time On-Chip Charge-Pump and Bootstrap Upper Bias Supplies DIS (Disable) Overrides Input Control Input Logic Thresholds Compatible with 5V to 5V Logic Levels Very Low Power Consumption Undervoltage Protection Pb-free Available Applications Medium/Large Voice Coil Motors Full Bridge Power Supplies Switching Power Amplifiers High Performance Motor Controls Noise Cancellation Systems Battery Powered Vehicles Peripherals U.P.S. Pinout BHB BHI DIS V SS BLI ALI AHI HDEL LDEL AHB HIP408A (PDIP, SOIC) TOP VIEW BHO BHS BLO BLS V DD V CC ALS ALO AHS AHO FN659 Rev 8.00 Page of 7

2 Application Block Diagram 80V V BHO BHS BHI BLO BLI HIP408A LOAD ALI AHI ALO AHS AHO GND GND Functional Block Diagram (/ HIP408A) 0 AHB HIGH VOLTAGE BUS 80V DC UNDER- VOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER AHO C BS V DD 6 AHS AHI 7 TURN-ON DELAY DIS 5 V CC D BS TO V DD (PIN 6) ALI 6 TURN-ON DELAY DRIVER 4 ALO ALS C BF +V DC BIAS SUPPLY HDEL 8 LDEL 9 V SS 4 FN659 Rev 8.00 Page of 7

3 Typical Application (PWM Mode Switching) 80V PWM INPUT V DIS BHB BHO BHI DIS 4 V SS 5 BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 0 AHB HIP408/HIP408A BHS BLO BLS V DD V CC ALS ALO AHS AHO V LOAD GND TO OPTIONAL CURRENT CONTROLLER - + 6V GND FN659 Rev 8.00 Page of 7

4 Absolute Maximum Ratings Supply Voltage, V DD and V CC V to 6V Logic I/O Voltages V to V DD +0.V Voltage on AHS, BHS V (Transient) to 80V (5 C to 5 C) Voltage on AHS, BHS V (Transient) to 70V (-55 C to 5 C) Voltage on ALS, BLS V (Transient) to +.0V (Transient) Voltage on AHB, BHB V AHS, BHS -0.V to V AHS, BHS +V DD Voltage on ALO, BLO V ALS, BLS -0.V to V CC +0.V Voltage on AHO, BHO V AHS, BHS -0.V to V AHB, BHB +0.V Input Current, HDEL and LDEL mA to 0mA Phase Slew Rate V/ns NOTE: All Voltages relative to V SS, unless otherwise specified. Operating Conditions Supply Voltage, V DD and V CC V to +5V Voltage on ALS, BLS V to +.0V Voltage on AHB, BHB V AHS, BHS +5V to V AHS, BHS +5V Input Current, HDEL and LDEL A to - A Operating Ambient Temperature Range C to 85 C Thermal Information Thermal Resistance (Typical, Note ) JA ( C/W) SOIC Package DIP Package Storage Temperature Range C to C Operating Max. Junction Temperature C Lead Temperature (Soldering 0s)) C (For SOIC - Lead Tips Only CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 C, Unless Otherwise Specified T J = 5 C T JS = -40 C TO 5 C PARAMETER SYMBOL TEST CONDITIONS SUPPLY CURRENTS AND CHARGE PUMPS MIN TYP MAX MIN MAX UNITS V DD Quiescent Current I DD All inputs = 0V ma V DD Operating Current I DDO Outputs switching f = 0kHz ma V CC Quiescent Current I CC All Inputs = 0V, I ALO = I BLO = A V CC Operating Current I CCO f = 0kHz, No Load ma AHB, BHB Quiescent Current - Qpump Output Current I AHB, I BHB All Inputs = 0V, I AHO = I BHO = 0 V DD = V CC = V AHB = V BHB = 0V A AHB, BHB Operating Current I AHBO, I BHBO f = 0kHz, No Load ma AHS, BHS, AHB, BHB Leakage Current I HLK V BHS = V AHS = 80V, V AHB = V BHB = 9V A AHB-AHS, BHB-BHS Qpump Output Voltage V AHB -V AHS I AHB = I AHB = 0, No Load V V BHB -V BHS INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current I IL V IN = 0V, Full Operating Conditions A High Level Input Current I IH V IN = 5V, Full Operating Conditions A TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V HDEL, V LDEL I HDEL = I LDEL = -00 A V GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage V OL I OUT = 00mA V High Level Output Voltage V CC -V OH I OUT = -00mA V Peak Pullup Current I O + V OUT = 0V A FN659 Rev 8.00 Page 4 of 7

5 Electrical Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 C, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS T J = 5 C T JS = -40 C TO 5 C MIN TYP MAX MIN MAX Peak Pulldown Current I O - V O UT = V A Undervoltage, Rising Threshold UV V Undervoltage, Falling Threshold UV V Undervoltage, Hysteresis HYS V UNITS Switching Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K, C L = 000pF. T J = 5 C T JS = -40 C TO 5 C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay T LPHL ns (ALI-ALO, BLI-BLO) Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) T HPHL ns T LPLH R HDEL = R LDEL = 0K ns T HPLH R HDEL = R LDEL = 0K ns Rise Time T R ns Fall Time T F ns Turn-on Input Pulse Width T PWIN-ON R HDEL = R LDEL = 0K ns Turn-off Input Pulse Width T PWIN-OFF R HDEL = R LDEL = 0K ns Turn-on Output Pulse Width T PWOUT-ON R HDEL = R LDEL = 0K ns Turn-off Output Pulse Width T PWOUT-OFF R HDEL = R LDEL = 0K ns Disable Turn-off Propagation Delay (DIS - Lower Outputs) T DISLOW ns Disable Turn-off Propagation Delay (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) T DISHIGH ns T DLPLH ns Refresh Pulse Width (ALO and BLO) T REF-PW ns Disable to Upper Enable (DIS - AHO and BHO) T UEN ns TRUTH TABLE INPUT OUTPUT ALI, BLI AHI, BHI U/V DIS ALO, BLO AHO, BHO X X X 0 0 X X X X 0 0 NOTE: X signifies that input can be either a or 0. FN659 Rev 8.00 Page 5 of 7

6 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0 A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. BHI B High-side Input. Logic level input that controls BHO driver (Pin 0). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin ) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). 4 V SS Chip negative supply, generally will be ground. 5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 8). If BHI (Pin ) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin ) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). 6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin ). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin ) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). 7 AHI A High-side Input. Logic level input that controls AHO driver (Pin ). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin ) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). 8 HDEL High-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.V. 0 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0 A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. AHO A High-side Output. Connect to gate of A High-side power MOSFET. AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 4 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 5 V CC Positive supply to gate drivers. Must be same potential as V DD (Pin 6). Connect to anodes of two bootstrap diodes. 6 V DD Positive supply to lower gate drivers. Must be same potential as V CC (Pin 5). De-couple this pin to V SS (Pin 4). 7 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 8 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 9 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 0 BHO B High-side Output. Connect to gate of B High-side power MOSFET. FN659 Rev 8.00 Page 6 of 7

7 Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT U/V = DIS = 0 T LPHL T HPHL XLI XHI XLO XHO T HPLH T LPLH T R (0% - 90%) T F (0% - 90%) FIGURE. INDEPENDENT MODE U/V = DIS = 0 XLI XHI = HI OR NOT CONNECTED XLO XHO (0% - 90%) (0% - 90%) FIGURE. BISTATE MODE U/V OR DIS T DLPLH T DIS T REF-PW XLI XHI XLO XHO T UEN FIGURE. DISABLE FUNCTION FN659 Rev 8.00 Page 7 of 7

8 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 C, Unless Otherwise Specified I DD SUPPLY CURRENT (ma) I DD SUPPLY CURRENT (ma) V DD SUPPLY VOLTAGE (V) SWITCHING FREQUENCY (khz) FIGURE 4. QUIESCENT I DD SUPPLY CURRENT vs V DD SUPPLY VOLTAGE FLOATING SUPPLY BIAS CURRENT (ma) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 000pF).5 SWITCHING FREQUENCY (khz) FIGURE 5. I DDO, NO-LOAD I DD SUPPLY CURRENT vs FREQUENCY (khz) 5.0 I CC SUPPLY CURRENT (ma) C 75 C 5 C 0 C -40 C SWITCHING FREQUENCY (khz) FIGURE 7. I CCO, NO-LOAD I CC SUPPLY CURRENT vs FREQUENCY (khz) TEMPERATURE -90 FLOATING SUPPLY BIAS CURRENT (ma) SWITCHING FREQUENCY (khz) LOW LEVEL INPUT CURRENT ( A) FIGURE 8. I AHB, I BHB, NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT I IL vs TEMPERATURE FN659 Rev 8.00 Page 8 of 7

9 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K and T A = 5 C, Unless Otherwise Specified NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) PROPAGATION DELAY (ns) FIGURE 0. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE 55 FIGURE. UPPER DISABLE TURN-OFF PROPAGATION DELAY T DISHIGH vs TEMPERATURE 80 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE. DISABLE TO UPPER ENABLE, T UEN, PROPAGATION DELAY vs TEMPERATURE 4 FIGURE. LOWER DISABLE TURN-OFF PROPAGATION DELAY T DISLOW vs TEMPERATURE REFRESH PULSE WIDTH (ns) PROPAGATION DELAY (ns) FIGURE 4. T REF-PW REFRESH PULSE WIDTH vs TEMPERATURE FIGURE 5. DISABLE TO LOWER ENABLE T DLPLH PROPAGATION DELAY vs TEMPERATURE FN659 Rev 8.00 Page 9 of 7

10 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K and T A = 5 C, Unless Otherwise Specified (Continued) PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE 6. UPPER TURN-OFF PROPAGATION DELAY T HPHL vs TEMPERATURE FIGURE 7. UPPER TURN-ON PROPAGATION DELAY T HPLH vs TEMPERATURE PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE 8. LOWER TURN-OFF PROPAGATION DELAY T LPHL vs TEMPERATURE FIGURE 9. LOWER TURN-ON PROPAGATION DELAY T LPLH vs TEMPERATURE.5.5 GATE DRIVE FALL TIME (ns) TURN-ON RISE TIME (ns) FIGURE 0. GATE DRIVE FALL TIME T F vs TEMPERATURE FIGURE. GATE DRIVE RISE TIME T R vs TEMPERATURE FN659 Rev 8.00 Page 0 of 7

11 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 C, Unless Otherwise Specified HDEL, LDEL INPUT VOLTAGE (V) V CC - V OH (mv) C 0 C 5 C 75 C FIGURE. V LDEL, V HDEL VOLTAGE vs TEMPERATURE 0 5 C BIAS SUPPLY VOLTAGE (V) FIGURE. HIGH LEVEL OUTPUT VOLTAGE V CC - V OH vs BIAS SUPPLY AND TEMPERATURE AT 00mA.5 V OL (mv) C 0 C 5 C 75 C GATE DRIVE SINK CURRENT (A) C 4 BIAS SUPPLY VOLTAGE (V) V DD, V CC, V AHB, V BHB (V) FIGURE 4. LOW LEVEL OUTPUT VOLTAGE V OL vs BIAS SUPPLY AND TEMPERATURE AT 00mA FIGURE 5. PEAK PULLDOWN CURRENT I O vs BIAS SUPPLY VOLTAGE GATE DRIVE SINK CURRENT (A) V DD, V CC, V AHB, V BHB (V) LOW VOLTAGE BIAS CURRENT (ma) ,000pF,000pF,000pF 00pF SWITCHING FREQUENCY (khz) FIGURE 6. PEAK PULLUP CURRENT I O+ vs BIAS SUPPLY VOLTAGE FIGURE 7. LOW VOLTAGE BIAS CURRENT I DD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE FN659 Rev 8.00 Page of 7

12 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K and T A = 5 C, Unless Otherwise Specified (Continued) LEVEL-SHIFT CURRENT ( A) SWITCHING FREQUENCY (khz) FIGURE 8. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE 9.0 UV+ BIAS SUPPLY VOLTAGE, V DD (V) UV- DEAD-TIME (ns) TEMPERATURE ( C) FIGURE 9. UNDERVOLTAGE LOCKOUT vs TEMPERATURE HDEL/LDEL RESISTANCE (k ) FIGURE 0. MINIMUM DEAD-TIME vs DEL RESISTANCE FN659 Rev 8.00 Page of 7

13 FN659 Rev 8.00 Page of 7 IN IN 5 ENABLE IN I R CONTROL LOGIC SECTION U CD4069UB U CD4069UB U CD4069UB U CD4069UB 9 U CD4069UB U 8 CD4069UB JMPR OUT/BLI JMPR IN+/ALI JMPR HEN/BHI JMPR4 IN-/AHI O R9 O +V JMPR5 R CW R4 CW + C6 DRIVER SECTION HIP4080A/8A U C4 4 BHB HEN/BHI DIS V SS BHO 0 BHS 9 BLO 8 BLS OUT/BLI IN+/ALI V DD V CC IN-/AHI HDEL LDEL ALS 4 ALO AHS 0 AHB AHO CR C C5 +V CR ALS R R R R4 CX BLS NOTES: FIGURE. HIP408A EVALUATION PC BOARD SCHEMATIC Q Q CY POWER SECTION R0 L C Q Q4 C8 R L C B+ AO BO COM. DEVICE CD4069UB PIN 7 = COM, PIN 4 = +V.. COMPONENTS L, L, C, C, CX, CY, R0, R, NOT SUPPLIED. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR - JMPR4. HIP408A

14 C C L L JMPR JMPR JMPR JMPR4 R Q JMPR5 R7 R8 R6 R GND U U CR C4 C R4 R R Q AO CR BO R R4 Q4 IR R0 O C8 C5 CX CY C7 C6 R9 IN IN BLS +V B+ DIS LDEL BHO BLO BLS Q COM ALS ALO AHO HDEL ALS + + HIP4080/8 O FIGURE. HIP408A EVALUATION BOARD SILKSCREEN FN659 Rev 8.00 Page 4 of 7

15 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN659.8 Updated Ordering Information Table on page. Added Revision History and About Intersil sections. Updated POD M0. from rev to rev. Changes since rev : Top View: Corrected "7. BSC" to "7.60/7.40" (no change from rev ; error was introduced in conversion) Changed "0.0 BSC" to "0.65/0.00" (no change from rev ; error was introduced in conversion) Side View: Changed ".80 BSC" to ".00/.60" (no change from rev ; error was introduced in conversion) Changed ".65 max" to ".65/.5" (no change from rev ; error was introduced in conversion) About Intersil Changed Note from "ANSI Y4.5M-98." to "ASME Y4.5M-994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN659 Rev 8.00 Page 5 of 7

16 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.5mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E4.6 will have a B dimension of inch ( mm). -B- A 0.00 (0.5) M C A A L B S A e C E C L e A C e B E0. (JEDEC MS-00-AD ISSUE D) 0 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e 0.00 BSC.54 BSC - e A 0.00 BSC 7.6 BSC 6 e B L N Rev. 0 /9 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN659 Rev 8.00 Page 6 of 7

17 Package Outline Drawing M0. 0 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev, / 0 INDEX AREA (0.0) M B M TOP VIEW SEATING PLANE BSC (0.0) M C A M B S 0.0 MAX 0.0 (0.004) 8 MAX x 45 SIDE VIEW DETAIL "X" NOTES: (0.60) (9.40mm) 0.7 BSC (.00). Dimensioning and tolerancing per ASME Y4.5M Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side.. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.5mm (0.00 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. The lead width as measured 0.6mm (0.4 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.04 inch) 8. Controlling dimension: MILLIMETER. 9. Dimensions in ( ) for reference only. 0. JEDEC reference drawing number: MS-0-AC. FN659 Rev 8.00 Page 7 of 7