Description PART NUMBER. HIP4080AIP -40 o C to +85 o C 20 Lead Plastic DIP. HIP4080AIB -40 o C to +85 o C 20 Lead Plastic SOIC (W)

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1 March 995 Features Drives N-Channel FET Full Bridge Including High Side Chop Capability Bootstrap Supply Max Voltage to 95VDC Drives 000pF Load at MHz in Free Air at +50 o C with Rise and Fall Times of Typically 0ns User-Programmable Dead Time Charge-Pump and Bootstrap Maintain Upper Bias Supplies DIS (Disable) Pin Pulls Gates Low Input Logic Thresholds Compatible with 5V to 5V Logic Levels Very Low Power Consumption Undervoltage Protection Applications Medium/Large Voice Coil Motors Full Bridge Power Supplies Class D Audio Power Amplifiers High Performance Motor Controls Noise Cancellation Systems Battery Powered Vehicles Peripherals U.P.S. Description 80V/.5A Peak, High Frequency Full Bridge FET Driver The HIP4080A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 0 lead plastic SOIC and DIP packages. The HIP4080A includes an input comparator, used to facilitate the hysteresis and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to MHz, the HIP4080A is well suited for driving Voice Coil Motors, switching amplifiers in class D high-frequency switching audio amplifiers and power supplies. HIP4080A can also drive medium voltage brush motors, and two HIP4080As can be used to drive high performance stepper motors, since the short minimum on-time can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. The similar HIP408A IC allows independent control of all 4 FETs in an Full Bridge configuration. The Application Note for the HIP4080A is AN9404. Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE HIP4080AIP -40 o C to +85 o C 0 Lead Plastic DIP HIP4080AIB -40 o C to +85 o C 0 Lead Plastic SOIC (W) Pinout Application Block Diagram HIP4080A (PDIP, SOIC) TOP VIEW 80V BHB 0 BHO V HEN 9 BHS DIS 8 BLO BHO V SS OUT BLS V DD HEN BHS BLO LOAD IN+ 6 5 V CC DIS IN- 7 4 ALS HIP4080A HDEL LDEL AHB AHS IN+ IN- AHS GND GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Corporation 999 File Number 658.4

2 Functional Block Diagram (/ HIP4080A) 0 AHB HIGH VOLTAGE BUS 80VDC UNDER- VOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER C BS V DD 6 AHS HEN DIS TURN-ON DELAY 5 V CC D BS TO V DD (PIN 6) OUT IN+ IN _ TURN-ON DELAY DRIVER 4 ALS C BF +VDC BIAS SUPPLY HDEL 8 LDEL 9 V SS 4 Typical Application (Hysteresis Mode Switching) 80V 6V IN V DIS BHB BHO HEN DIS 4 V SS 5 OUT 6 IN+ 7 IN- 8 HDEL HIP4080A/HIP4080 BHS BLO BLS V DD V CC ALS V LOAD 9 0 LDEL AHB AHS GND - + 6V GND

3 Absolute Maximum Ratings Supply Voltage, V DD and V CC V to 6V Logic I/O Voltages V to V DD +0.V Voltage on AHS, BHS V (Transient) to 80V (5 o C to 5 o C) Voltage on AHS, BHS V (Transient) to 70V (-55 o C to 5 o C) Voltage on ALS, BLS V (Transient) to +.0V (Transient) Voltage on AHB, BHB V AHS, BHS -0.V to V AHS, BHS +V DD Voltage on, BLO V ALS, BLS -0.V to V CC +0.V Voltage on, BHO V AHS, BHS -0.V to V AHB, BHB +0.V Input Current, HDEL and LDEL mA to 0mA Phase Slew Rate V/ns NOTE: All Voltages relative to V SS, unless otherwise specified. Specifications HIP4080A Thermal Information Thermal Resistance θ JA SOIC Package o C/W DIP Package o C/W Maximum Power Dissipation at +85 o C SOIC Package mW DIP Package mW Storage Temperature Range o C to +50 o C Operating Max. Junction Temperature o C Lead Temperature (Soldering 0s) o C (For SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Supply Voltage, V DD and V CC V to +5V Voltage on ALS, BLS V to +.0V Voltage on AHB, BHB V AHS, BHS +5V to V AHS, BHS +5V Input Current, HDEL and LDEL µA to -50µA Operating Ambient Temperature Range o C to +85 o C Electrical Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 o C, Unless Otherwise Specified T J = +5 o C T J = - 40 o C TO +5 o C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS AND CHARGE PUMPS V DD Quiescent Current I DD IN- =.5V, Other Inputs = 0V ma V DD Operating Current I DDO Outputs switching f = 500kHz, No Load ma V CC Quiescent Current I CC IN- =.5V, Other Inputs = 0V, µa I = I BLO = 0 V CC Operating Current I CCO f = 500kHz, No Load ma AHB, BHB Quiescent Current - Qpump Output Current I AHB, I BHB IN- =.5V, Other Inputs = 0V, I = I BHO = 0, V DD = V CC =V AHB = V BHB = 0V µa AHB, BHB Operating Current I AHBO, I BHBO f = 500kHz, No Load ma AHS, BHS, AHB, BHB Leakage Current I HLK V BHS = V AHS = 80V, µa V AHB = V BHB = 9V AHB-AHS, BHB-BHS Qpump Output Voltage V AHB - V AHS I AHB = I AHB = 0, No Load V V BHB - V BHS INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage V OS Over Common Mode Voltage Range mv Input Bias Current I IB µa Input Offset Current I OS µa Input Common Mode Voltage Range CMVR - V DD -.5 V DD -.5 Voltage Gain AVOL V/mV OUT High Level Output Voltage V OH IN+ > IN-, I OH = -50µA V DD V DD V - V OUT Low Level Output Voltage V OL IN+ < IN-, I OL = +50µA V Low Level Output Current I OL V OUT = 6V ma High Level Output Current I OH V OUT = 6V ma INPUT PINS: DIS Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current I IL V IN = 0V, Full Operating Conditions µa High Level Input Current I IH V IN = 5V, Full Operating Conditions µa

4 Specifications HIP4080A Electrical Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 o C, Unless Otherwise Specified (Continued) PARAMETERS SYMBOL TEST CONDITIONS T J = +5 o C INPUT PINS: HEN Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current I IL V IN = 0V, Full Operating Conditions µa High Level Input Current I IH V IN = 5V, Full Operating Conditions µa TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V HDEL, V I HDEL = I LDEL = -00µA V GATE DRIVER OUTPUT PINS:, BLO,, AND BHO Low Level Output Voltage V OL I OUT = 00mA V High Level Output Voltage V CC - V OH I OUT = -00mA V Peak Pullup Current I O + V OUT = 0V A Peak Pulldown Current I O - V OUT = V A Under Voltage, Rising Threshold UV V Under Voltage, Falling Threshold UV V Under Voltage, Hysteresis HYS V Switching Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K, C L = 000pF, and T A = +5 o C, Unless Otherwise Specified T J = +5 o C T J = - 40 o C TO +5 o C MIN TYP MAX MIN MAX T J = - 40 o C TO +5 o C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (IN+/IN- to /BLO) T LPHL ns Upper Turn-off Propagation Delay (IN+/IN- to /BHO) T HPHL ns Lower Turn-on Propagation Delay (IN+/IN- to /BLO) T LPLH ns Upper Turn-on Propagation Delay (IN+/IN- to /BHO) T HPLH ns Rise Time T R ns Fall Time T F ns Turn-on Input Pulse Width T PWIN-ON ns Turn-off Input Pulse Width T PWIN-OFF ns Disable Turn-off Propagation Delay T DISLOW ns (DIS - Lower Outputs) Disable Turn-off Propagation Delay T DISHIGH ns (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay T DLPLH ns (DIS - and BLO) Refresh Pulse Width ( and BLO) T REF-PW ns Disable to Upper Enable (DIS - and BHO) T UEN ns HEN-, BHO Turn-off, Propagation Delay T HEN-PHL R HDEL = R LDEL = 0K ns HEN-, BHO Turn-on, Propagation Delay T HEN-PLH R HDEL = R LDEL = 0K ns TRUTH TABLE INPUT OUTPUT IN+ > IN- HEN U/V DIS BLO BHO X X X X X X UNITS 4

5 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put and BHO drivers (Pins and 0) in low output state. When HEN is high and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). An internal 00µA pull-up to V DD will hold HEN high, so no connection is required if high-side and low-side outputs are to be controlled by IN+/INinputs. DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). An internal 00µA pull-up to V DD will hold DIS high if this pin is not driven. 4 V SS Chip negative supply, generally will be ground. 5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis. 6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then and BHO are low level outputs and BLO and are high level outputs. If IN+ is less than IN- then and BHO are high level outputs and BLO and are low level outputs. DIS (Pin ) high level will override IN+/IN- control for all outputs. HEN (Pin ) low level will override IN+/IN- control of and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). 7 IN- Inverting input of control comparator. See IN+ (Pin 6) description. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.V. 0 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. A High-side Output. Connect to gate of A High-side power MOSFET. AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. A Low-side Output. Connect to gate of A Low-side power MOSFET. 4 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 5 V CC Positive supply to gate drivers. Must be same potential as V DD (Pin 6). Connect to anodes of two bootstrap diodes. 6 V DD Positive supply to lower gate drivers. Must be same potential as V CC (Pin 5). De-couple this pin to V SS (Pin 4). 7 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 8 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 9 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 0 BHO B High-side Output. Connect to gate of B High-side power MOSFET. 5

6 Timing Diagrams T DT U/V = DIS HEN 0 T HPHL T LPLH IN+ > IN- BLO BHO T T HPLH LPHL T T R T DT F (0% - 90%) (90% - 0%) FIGURE. BISTATE MODE T HEN-PHL T HEN-PLH U/V = DIS 0 HEN IN+ > IN- BLO BHO FIGURE. HIGH SIDE CHOP MODE T DLPLH T DIS U/V or DIS T REF-PW HEN IN+ > IN- BLO BHO T UEN FIGURE. DISABLE FUNCTION 6

7 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 o C, Unless Otherwise Specified I DD SUPPLY CURRENT (ma) I DD SUPPLY CURRENT (ma) V DD SUPPLY VOLTAGE (V) FIGURE 4. QUIESCENT I DD SUPPLY CURRENT vs V DD SUPPLY VOLTAGE SWITCHING FREQUENCY (khz) FIGURE 5. I DDO NO-LOAD I DD SUPPLY CURRENT vs FRE- QUENCY (khz) FLOATING SUPPLY BIAS CURRENT (ma) SWITCHING FREQUENCY (khz) I CC SUPPLY CURRENT (ma) o C +75 o C o C 0 o C.0-40 o C SWITCHING FREQUENCY (khz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 000pF).5 FIGURE 7. I CCO, NO-LOAD I CC SUPPLY CURRENT vs FRE- QUENCY (khz) TEMPERATURE FLOATING SUPPLY BIAS CURRENT (ma) COMPARATOR INPUT CURRENT (µa) SWITCHING FREQUENCY (khz) FIGURE 8. I AHB, I BHB NO-LOAD FLOATING SUPPLY BIAS CUR- RENT vs FREQUENCY FIGURE 9. COMPARATOR INPUT CURRENT I L vs TEMPERA- TURE AT V CM = 5 V 7

8 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 o C, Unless Otherwise Specified (Continued) LOW LEVEL INPUT CURRENT (µa) LOW LEVEL INPUT CURRENT (µa) FIGURE 0. DIS LOW LEVEL INPUT CURRENT I IL vs TEMPERA- TURE NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) FIGURE. HEN LOW LEVEL INPUT CURRENT I IL vs TEMPER- ATURE FIGURE. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE 55 FIGURE. UPPER DISABLE TURN-OFF PROPAGATION DELAY T DISHIGH vs TEMPERATURE FIGURE 4. DISABLE TO UPPER ENABLE T UEN PROPAGATION DELAY vs TEMPERATURE FIGURE 5. LOWER DISABLE TURN-OFF PROPAGATION DELAY T DISLOW vs TEMPERATURE 8

9 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K, and T A = +5 o C, Unless Otherwise Specified REFRESH PULSE WIDTH (ns) FIGURE 6. T REF-PW REFRESH PULSE WIDTH vs TEMPERA- TURE FIGURE 7. DISABLE TO LOWER ENABLE TDLPLH PROPAGA- TION DELAY vs TEMPERATURE FIGURE 8. UPPER TURN-OFF PROPAGATION DELAY T HPHL vs TEMPERATURE FIGURE 9. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE FIGURE 0. LOWER TURN-OFF PROPAGATION DELAY T LPHL vs TEMPERATURE FIGURE. LOWER TURN-ON PROPAGATION DELAY T LPLH vs TEMPERATURE 9

10 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 o C, Unless Otherwise Specified.5.5 GATE DRIVE FALL TIME (ns) TURN-ON RISE TIME (ns) FIGURE. GATE DRIVE FALL TIME T F vs TEMPERATURE FIGURE. GATE DRIVE RISE TIME T R vs TEMPERATURE HDEL, LDEL INPUT VOLTAGE (V) V CC - V OH (mv) o C 0 o C +5 o C +75 o C FIGURE 4. V LDEL, V HDEL VOLTAGE vs TEMPERATURE +5 o C BIAS SUPPLY VOLTAGE (V) FIGURE 5. HIGH LEVEL OUTPUT VOLTAGE, V CC - V OH vs BIAS SUPPLY AND TEMPERATURE AT 00µA V OL (mv) o C 0 o C +5 o C +75 o C +5 o C 4 BIAS SUPPLY VOLTAGE (V) FIGURE 6. LOW LEVEL OUTPUT VOLTAGE V OL vs BIAS SUPPLY AND TEMPERATURE AT 00µA GATE DRIVE SINK CURRENT (A) V CC, V DD, V AHG, V BHB (V) FIGURE 7. PEAK PULLDOWN CURRENT I O- BIAS SUPPLY VOLTAGE 0

11 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 o C, Unless Otherwise Specified (Continued) GATE DRIVE SINK CURRENT (A) V CC, V DD, V ABH, V BHB (V) FIGURE 8. PEAK PULLUP CURRENT I O+ vs SUPPLY VOLTAGE 000 LOW VOLTAGE BIAS CURRENT (ma) ,000,000, SWITCHING FREQUENCY (khz) FIGURE 9. LOW VOLTAGE BIAS CURRENT I DD AND I CC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE 9 LEVEL-SHIFT CURRENT (µa) BIAS SUPPLY VOLTAGE, V DD (V) UV+ UV SWITCHING FREQUENCY (khz) FIGURE 0. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE TEMPERATURE ( o C) FIGURE. UNDERVOLTAGE LOCKOUT vs TEMPERATURE 50 0 DEAD-TIME (ns) HDEL/LDEL RESISTANCE (kω) FIGURE. MINIMUM DEAD-TIME vs DEL RESISTANCE

12 IN IN +V POWER SECTION B+ CONTROL LOGIC SECTION 5 U CD4069UB U CD4069UB U CD4069UB U CD4069UB 6 0 R9 JMPR OUT/BLI JMPR IN+/ALI JMPR HEN/BHI JMPR4 IN-/AHI JMPR5 R CW + C6 R4 CW DRIVER SECTION HIP4080A/8A U C4 4 BHB HEN/BHI DIS V SS BHO 0 BHS 9 BLO 8 BLS OUT/BLI IN+/ALI V DD V CC IN-/AHI ALS HDEL LDEL AHB AHS CR C +V CR R R R R4 CX Q Q CY R0 Q L C Q4 C8 R L C AO BO HIP4080A C5 COM ALS BLS NOTES:. DEVICE CD4069UB PIN 7 = COM. PIN 4 = +V.. COMPONENTS L, L, C, C, CX, CY, R0, R, ARE NOT SUPPLIED. REFER TO APPLICATION NOTE FOR HELP IN DE- TERMINING JMPR - JMPR4 JUMPER LOCATIONS. FIGURE. HIP4080A EVALUATION PC BOARD SCHEMATIC

13 GND +V B+ COM IR IN O IN R9 C7 JMPR5 R7 R8 R6 C6 + + U U DIS JMPR JMPR JMPR JMPR4 O LDEL CR HIP4080/8 C4 BHO BLO BLS ALS C C8 Q Q R R4 R Q Q4 R L L C C AO BO HIP4080A ALS HDEL CR C5 CX CY BLS R R4 R0 R FIGURE 4. HIP4080A EVALUATION BOARD SILKSCREEN

14 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B N N/ B D e D -C- -A- NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.5mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E4.6 will have a B dimension of inch ( mm). E -B- A 0.00 (0.5) M C A A L B S A e C E C L e A e B C E0. (JEDEC MS-00-AD ISSUE D) 0 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e 0.00 BSC.54 BSC - e A 0.00 BSC 7.6 BSC 6 e B L N Rev. 0 /9 4

15 Small Outline Plastic Packages (SOIC) HIP4080A N INDEX AREA e D B 0.5(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.5(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.5mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.6mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.04 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α L M h x 45 o C M0. (JEDEC MS-0-AC ISSUE C) 0 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e BSC.7 BSC - H h L N α 0 o 8 o 0 o 8 o - Rev. 0 /9 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 88, Mail Stop 5-04 Melbourne, FL 90 TEL: () FAX: () EUROPE Intersil SA Mercure Center 00, Rue de la Fusee 0 Brussels, Belgium TEL: ().74. FAX: () ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 0 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) FAX: (886)