DATASHEET HIP4080A. Features. Applications. Ordering Information. Pinout. 80V/2.5A Peak, High Frequency Full Bridge FET Driver

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1 DATASHEET HIP4080A 80V/.5A Peak, High Frequency Full Bridge FET Driver The HIP4080A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 0 lead plastic SOIC and DIP packages. The HIP4080A includes an input comparator, used to facilitate the hysteresis and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to MHz, the HIP4080A is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies. HIP4080A can also drive medium voltage brush motors, and two HIP4080As can be used to drive high performance stepper motors, since the short minimum on-time can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximize control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. The similar HIP408A IC allows independent control of all 4 FETs in a Full Bridge configuration. The Application Note for the HIP4080A is AN9404. Ordering Information PART NUMBER HIP4080AIPZ (Note ) TEMPERATURE RANGE ( C) PACKAGE -40 to Ld PDIP (Pb-Free) PKG. DWG. # E0. HIP4080AIP -40 to Ld PDIP E0. HIP4080AIB -40 to Ld SOIC M0. HIP4080AIBZ (Note ) -40 to Ld SOIC (Pb-Free) M0. NOTES:. Intersil Pb-Free products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-Free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-00B.. Add T suffix for Tape and Reel packing option. HIP4080AIP not available in Tape and Reel. Features FN658 Rev.7.00 Drives N-Channel FET Full Bridge Including High Side Chop Capability Bootstrap Supply Max Voltage to 95VDC Drives 000pF Load at MHz in Free Air at +50 C with Rise and Fall Times of Typically 0ns User-Programmable Dead Time Charge-Pump and Bootstrap Maintain Upper Bias Supplies DIS (Disable) Pin Pulls Gates Low Input Logic Thresholds Compatible with 5V to 5V Logic Levels Very Low Power Consumption Undervoltage Protection Pb-Free Available as an Option Applications Medium/Large Voice Coil Motors Full Bridge Power Supplies Switching Power Amplifiers High Performance Motor Controls Noise Cancellation Systems Battery Powered Vehicles Peripherals U.P.S. Pinout BHB HEN DIS V SS OUT IN+ IN- HDEL LDEL AHB HIP4080A (PDIP, SOIC) TOP VIEW BHO BHS BLO BLS V DD V CC ALS AHS AHO FN658 Rev.7.00 Page of 7

2 Application Block Diagram 80V V BHO BHS HEN BLO DIS HIP4080A LOAD IN+ IN- AHS AHO GND GND Functional Block Diagram (/ HIP4080A) 0 AHB HIGH VOLTAGE BUS 80VDC UNDER- VOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER AHO C BS V DD 6 AHS HEN TURN-ON DELAY DIS 5 V CC D BS TO V DD (PIN 6) OUT IN+ IN _ TURN-ON DELAY DRIVER 4 ALS C BF +VDC BIAS SUPPLY HDEL 8 LDEL 9 V SS 4 FN658 Rev.7.00 Page of 7

3 Typical Application (Hysteresis Mode Switching) 80V 6V IN V DIS BHB BHO HEN DIS 4 V SS 5 OUT 6 IN+ 7 IN- 8 HDEL HIP4080A/HIP4080 BHS BLO BLS V DD V CC ALS V LOAD 9 LDEL AHS 0 AHB AHO GND - + 6V GND FN658 Rev.7.00 Page of 7

4 Absolute Maximum Ratings Supply Voltage, V DD and V CC V to 6V Logic I/O Voltages V to V DD +0.V Voltage on AHS, BHS V (Transient) to 80V (5 C to 5 C) Voltage on AHS, BHS V (Transient) to 70V (-55 C to 5 C) Voltage on ALS, BLS V (Transient) to +.0V (Transient) Voltage on AHB, BHB V AHS, BHS -0.V to V AHS, BHS +V DD Voltage on, BLO V ALS, BLS -0.V to V CC +0.V Voltage on AHO, BHO V AHS, BHS -0.V to V AHB, BHB +0.V Input Current, HDEL and LDEL mA to 0mA Phase Slew Rate V/ns All Voltages relative to V SS, unless otherwise specified. Thermal Information Thermal Resistance (Typical, Note ) JA ( C/W) SOIC Package PDIP Package Maximum Power Dissipation at +85 C SOIC Package mW PDIP Package mW Storage Temperature Range C to +50 C Operating Max. Junction Temperature C Lead Temperature (Soldering 0s) C (For SOIC - Lead Tips Only) Operating Conditions Supply Voltage, V DD and V CC V to +5V Voltage on ALS, BLS V to +.0V Voltage on AHB, BHB V AHS, BHS +5V to V AHS, BHS +5V Input Current, HDEL and LDEL A to -50 A Operating Ambient Temperature Range C to +85 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB79 for details. Electrical Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 C, Unless Otherwise Specified T J = +5 C T J = - 40 C TO +5 C PARAMETERS SYMBOL TEST CONDITIONS SUPPLY CURRENTS AND CHARGE PUMPS MIN TYP MAX MIN MAX UNITS V DD Quiescent Current I DD IN- =.5V, Other Inputs = 0V ma V DD Operating Current I DDO Outputs switching f = 500kHz, No Load ma V CC Quiescent Current I CC IN- =.5V, Other Inputs = 0V, I = I BLO = A V CC Operating Current I CCO f = 500kHz, No Load ma AHB, BHB Quiescent Current - Qpump Output Current I AHB, I BHB IN- =.5V, Other Inputs = 0V, I AHO =I BHO = 0, V DD = V CC =V AHB = V BHB = 0V A AHB, BHB Operating Current I AHBO, I BHBO f = 500kHz, No Load ma AHS, BHS, AHB, BHB Leakage Current I HLK V BHS = V AHS = 80V, V AHB = V BHB = 9V A AHB-AHS, BHB-BHS Qpump Output Voltage V AHB - V AHS V BHB - V BHS I AHB = I AHB = 0, No Load V INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage V OS Over Common Mode Voltage Range mv Input Bias Current I IB A Input Offset Current I OS A Input Common Mode Voltage Range CMVR - V DD -.5 V DD -.5 V FN658 Rev.7.00 Page 4 of 7

5 Electrical Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 C, Unless Otherwise Specified (Continued) T J = +5 C T J = - 40 C TO +5 C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Voltage Gain AVOL V/mV OUT High Level Output Voltage V OH IN+ > IN-, I OH = -50 A V DD V DD V OUT Low Level Output Voltage V OL IN+ < IN-, I OL = +50 A V Low Level Output Current I OL V OUT = 6V ma High Level Output Current I OH V OUT = 6V ma INPUT PINS: DIS Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current I IL V IN = 0V, Full Operating Conditions A High Level Input Current I IH V IN = 5V, Full Operating Conditions A INPUT PINS: HEN Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current I IL V IN = 0V, Full Operating Conditions A High Level Input Current I IH V IN = 5V, Full Operating Conditions A TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V HDEL, V I HDEL = I LDEL = -00 A V GATE DRIVER OUTPUT PINS:, BLO, AHO, AND BHO Low Level Output Voltage V OL I OUT = 00mA V High Level Output Voltage V CC - V OH I OUT = -00mA V Peak Pullup Current I O + V OUT = 0V A Peak Pulldown Current I O - V OUT = V A Under Voltage, Rising Threshold UV V Under Voltage, Falling Threshold UV V Under Voltage, Hysteresis HYS V FN658 Rev.7.00 Page 5 of 7

6 Switching Specifications V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K, C L = 000pF, and T A = +5 C, Unless Otherwise Specified T J = +5 C T J = - 40 C TO +5 C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (IN+/IN- to /BLO) T LPHL ns Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) T HPHL ns Lower Turn-on Propagation Delay (IN+/IN- to /BLO) T LPLH ns Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) T HPLH ns Rise Time T R ns Fall Time T F ns Turn-on Input Pulse Width T PWIN-ON ns Turn-off Input Pulse Width T PWIN-OFF ns Disable Turn-off Propagation Delay (DIS - Lower Outputs) Disable Turn-off Propagation Delay (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay (DIS - and BLO) T DISLOW ns T DISHIGH ns T DLPLH ns Refresh Pulse Width ( and BLO) T REF-PW ns Disable to Upper Enable (DIS - AHO and BHO) T UEN ns HEN-AHO, BHO Turn-off, Propagation Delay T HEN-PHL R HDEL = R LDEL = 0K ns HEN-AHO, BHO Turn-on, Propagation Delay T HEN-PLH R HDEL = R LDEL = 0K ns TRUTH TABLE INPUT OUTPUT IN+ > IN- HEN U/V DIS AHO BLO BHO X X X X X X FN658 Rev.7.00 Page 6 of 7

7 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0 A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins and 0) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 5V (no greater than V DD ). 4 V SS Chip negative supply, generally will be ground. 5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis. 6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin ) high level will override IN+/IN- control for all outputs. HEN (Pin ) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). 7 IN- Inverting input of control comparator. See IN+ (Pin 6) description. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.V. 0 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0 A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. AHO A High-side Output. Connect to gate of A High-side power MOSFET. AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. A Low-side Output. Connect to gate of A Low-side power MOSFET. 4 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 5 V CC Positive supply to gate drivers. Must be same potential as V DD (Pin 6). Connect to anodes of two bootstrap diodes. 6 V DD Positive supply to lower gate drivers. Must be same potential as V CC (Pin 5). De-couple this pin to V SS (Pin 4). 7 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 8 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 9 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 0 BHO B High-side Output. Connect to gate of B High-side power MOSFET. FN658 Rev.7.00 Page 7 of 7

8 Timing Diagrams T DT U/V = DIS HEN 0 T HPHL T LPLH IN+ > IN- AHO BLO BHO T T HPLH LPHL T T R T DT F (0% - 90%) (90% - 0%) FIGURE. BISTATE MODE T HEN-PHL T HEN-PLH U/V = DIS 0 HEN IN+ > IN- AHO BLO BHO FIGURE. HIGH SIDE CHOP MODE T DLPLH T DIS T REF-PW U/V or DIS HEN IN+ > IN- AHO BLO BHO T UEN FIGURE. DISABLE FUNCTION FN658 Rev.7.00 Page 8 of 7

9 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 C, Unless Otherwise Specified I DD SUPPLY CURRENT (ma) I DD SUPPLY CURRENT (ma) V DD SUPPLY VOLTAGE (V) SWITCHING FREQUENCY (khz) FIGURE 4. QUIESCENT I DD SUPPLY CURRENT vs V DD SUPPLY VOLTAGE FIGURE 5. I DDO NO-LOAD I DD SUPPLY CURRENT vs FREQUENCY (khz) C FLOATING SUPPLY BIAS CURRENT (ma) I CC SUPPLY CURRENT (ma) C +5 C 0 C -40 C SWITCHING FREQUENCY (khz) SWITCHING FREQUENCY (khz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 000pF) FIGURE 7. I CCO, NO-LOAD I CC SUPPLY CURRENT vs FREQUENCY (khz) TEMPERATURE FLOATING SUPPLY BIAS CURRENT (ma) COMPARATOR INPUT CURRENT ( A) SWITCHING FREQUENCY (khz) FIGURE 8. I AHB, I BHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FIGURE 9. COMPARATOR INPUT CURRENT I L vs TEMPERATURE AT V CM = 5V FN658 Rev.7.00 Page 9 of 7

10 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 C, Unless Otherwise Specified (Continued) LOW LEVEL INPUT CURRENT ( A) LOW LEVEL INPUT CURRENT ( A) FIGURE 0. DIS LOW LEVEL INPUT CURRENT I IL vs TEMPERATURE NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) FIGURE. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE FIGURE. HEN LOW LEVEL INPUT CURRENT I IL vs TEMPERATURE PROPAGATION DELAY (ns) FIGURE. UPPER DISABLE TURN-OFF PROPAGATION DELAY T DISHIGH vs TEMPERATURE PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE 4. DISABLE TO UPPER ENABLE T UEN PROPAGATION DELAY vs TEMPERATURE FIGURE 5. LOWER DISABLE TURN-OFF PROPAGATION DELAY T DISLOW vs TEMPERATURE FN658 Rev.7.00 Page 0 of 7

11 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K, and T A = +5 C, Unless Otherwise Specified REFRESH PULSE WIDTH (ns) PROPAGATION DELAY (ns) FIGURE 6. T REF-PW REFRESH PULSE WIDTH vs TEMPERATURE FIGURE 7. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE 8. UPPER TURN-OFF PROPAGATION DELAY T HPHL vs TEMPERATURE FIGURE 9. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) FIGURE 0. LOWER TURN-OFF PROPAGATION DELAY T LPHL vs TEMPERATURE FIGURE. LOWER TURN-ON PROPAGATION DELAY T LPLH vs TEMPERATURE FN658 Rev.7.00 Page of 7

12 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 C, Unless Otherwise Specified.5.5 GATE DRIVE FALL TIME (ns) TURN-ON RISE TIME (ns) FIGURE. GATE DRIVE FALL TIME T F vs TEMPERATURE FIGURE. GATE DRIVE RISE TIME T R vs TEMPERATURE HDEL, LDEL INPUT VOLTAGE (V) V CC - V OH (mv) C 0 C +5 C +75 C FIGURE 4. V LDEL, V HDEL VOLTAGE vs TEMPERATURE +5 C BIAS SUPPLY VOLTAGE (V) FIGURE 5. HIGH LEVEL OUTPUT VOLTAGE, V CC - V OH vs BIAS SUPPLY AND TEMPERATURE AT 00 A V OL (mv) C 0 C +5 C +75 C +5 C 4 BIAS SUPPLY VOLTAGE (V) FIGURE 6. LOW LEVEL OUTPUT VOLTAGE V OL vs BIAS SUPPLY AND TEMPERATURE AT 00 A GATE DRIVE SINK CURRENT (A) V CC, V DD, V AHG, V BHB (V) FIGURE 7. PEAK PULLDOWN CURRENT I O- BIAS SUPPLY VOLTAGE FN658 Rev.7.00 Page of 7

13 Typical Performance Curves V DD = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A = +5 C, Unless Otherwise Specified (Continued) GATE DRIVE SINK CURRENT (A) V CC, V DD, V ABH, V BHB (V) FIGURE 8. PEAK PULLUP CURRENT I O+ vs SUPPLY VOLTAGE LOW VOLTAGE BIAS CURRENT (ma) ,000,000, SWITCHING FREQUENCY (khz) FIGURE 9. LOW VOLTAGE BIAS CURRENT I DD AND I CC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE LEVEL-SHIFT CURRENT ( A) BIAS SUPPLY VOLTAGE, V DD (V) UV+ UV SWITCHING FREQUENCY (khz) FIGURE 0. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE TEMPERATURE ( C) FIGURE. UNDERVOLTAGE LOCKOUT vs TEMPERATURE 50 0 DEAD-TIME (ns) HDEL/LDEL RESISTANCE (k ) FIGURE. MINIMUM DEAD-TIME vs DEL RESISTANCE FN658 Rev.7.00 Page of 7

14 FN658 Rev.7.00 Page 4 of 7 IN IN CONTROL LOGIC SECTION 5 U CD4069UB U CD4069UB U CD4069UB U CD4069UB 6 0 R9 JMPR OUT/BLI JMPR IN+/ALI JMPR HEN/BHI JMPR4 IN-/AHI +V JMPR5 R CW R4 CW + C6 DRIVER SECTION HIP4080A/8A U C4 4 BHB HEN/BHI DIS V SS BHO 0 BHS 9 BLO 8 BLS OUT/BLI IN+/ALI V DD V CC 6 5 +V 7 IN-/AHI ALS HDEL LDEL AHB AHS AHO CR C C5 CR ALS CX R R R R4 BLS FIGURE. HIP4080A EVALUATION PC BOARD SCHEMATIC CY POWER SECTION Q Q R0 L C Q Q4 C8 R NOTES:. DEVICE CD4069UB PIN 7 = COM. PIN 4 = +V.. COMPONENTS L, L, C, C, CX, CY, R0, R, ARE NOT SUPPLIED. REFER TO APPLICATION NOTE FOR HELP IN DETERMINING JMPR - JMPR4 JUMPER LOCATIONS. L C B+ AO BO COM HIP4080A

15 C AO L C JMPR JMPR JMPR JMPR4 R Q JMPR5 R7 R8 R6 R L GND +V B+ U U CR C4 C R4 BO R R Q CR R R4 BLS Q4 R0 IR O C8 C5 CX CY C7 C6 R9 IN IN + + DIS LDEL BHO Q COM BLO BLS ALS AHO HDEL HIP4080/8 O ALS FIGURE. HIP4080A EVALUATION BOARD SILKSCREEN FN658 Rev.7.00 Page 5 of 7

16 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.5mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E4.6 will have a B dimension of inch ( mm). -B- A 0.00 (0.5) M C A A L B S A e C E C L e A C e B E0. (JEDEC MS-00-AD ISSUE D) 0 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e 0.00 BSC.54 BSC - e A 0.00 BSC 7.6 BSC 6 e B L N Rev. 0 /9 FN658 Rev.7.00 Page 6 of 7

17 N Small Outline Plastic Packages (SOIC) INDEX AREA e D B 0.5(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H A µ 0.5(0.00) M B 0.0(0.004) L M h x 45 o C M0. (JEDEC MS-0-AC ISSUE C) 0 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e BSC.7 BSC - H h L N o 8 o 0 o 8 o - Rev. /0 NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.5mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.6mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.04 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN658 Rev.7.00 Page 7 of 7