MP V High Frequency Half-Bridge Gate Driver

Transcription

1 The Future of Analog IC Technology MP8 V High Frequency Half-Bridge Gate Driver DESCRIPTION The MP8 is a high frequency, V half bridge N-channel power MOSFET driver. Its low side and high side driver channels are independently controlled and matched with less than 5ns in time delay. Under voltage lock-out on both high side and low side supplies force their outputs low in case of insufficient supply. The integrated bootstrap diode reduces external component count. FEATURES Drives N-channel MOSFET half bridge V V BST voltage range On-chip bootstrap diode Typical 6ns propagation delay time Less than 5ns gate drive matching Drive nf load with ns/9ns rise/fall times with V VDD TTL compatible input Less than 5A quiescent current UVLO for both high side and low side In SOIC8 EPAD and 3 3mm QFN8 Packages APPLICATIONS Telecom half bridge power supplies Avionics DC-DC converters Two-switch forward converters Active clamp forward converters All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. MPS and The Future of Analog IC Technology are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION +V 48V VDD BST SECONDARY SIDE CIRCUIT PWM CONTROLLER INH INL CONTROL DRIVE HI DRIVE LO DRVH SW DRVL MP8 VSS ISOLATION AND FEEDBACK MP8 Rev..

2 ORDERING INFORMATION Part Number* Package Top Marking Free Air Temperature (T A ) MP8HN SOIC8EP MP8HN -4C to + 5C MP8HQ QFN8 (3x 3mm) ABN -4C to + 5C * For Tape & Reel, add suffix Z (e.g. MP8HN Z); For RoHS compliant packaging, add suffix LF; (e.g. MP8HN LF Z) For Tape & Reel, add suffix Z (e.g. MP8HQ Z); For RoHS compliant packaging, add suffix LF; (e.g. MP8HQ LF Z) PACKAGE REFERENCE TOP VIEW TOP VIEW VDD 8 DRVL VDD 8 DRVL BST 7 VSS BST 7 VSS DRVH SW INL INH DRVH SW INL INH EXPOSED PAD ON BACKSIDE SOIC8EP QFN8 ABSOLUTE MAXIMUM RATINGS () Supply Voltage (V DD )...-.3V to +8V SW Voltage (V SW )...-5.V to V BST Voltage (V BST )...-.3V to V BST to SW...-.3V to +8V DRVH to SW...-.3V to +8V All Other Pins V to (V DD +.3V) Continuous Power Dissipation (T A =+5 C) () SOIC8 (Exposed Pad)....6W QFN8 (3x3)....5W Junction Temperature...5C Lead Temperature...6C Storage Temperature C to +5C Recommended Operating Conditions (3) Supply Voltage V DD...+9.V to 6.V SW Voltage (V SW )...-.V to V-V DD SW slew rate...<5v/nsec Operating Junct. Temp (T J )... -4C to +4C Thermal Resistance (4) θ JA θ JC SOIC8 (Exposed Pad) C/W QFN8 (3x3) C/W Notes: ) Exceeding these ratings may damage the device. ) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-toambient thermal resistance θ JA, and the ambient temperature T A. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX)=(T J (MAX)- T A )/ θ JA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD5-7, 4-layer PCB. MP8 Rev..

3 ELECTRICAL CHARACTERISTICS V DD = V BST -V SW =V, V SS =V SW = V, No load at DRVH and DRVL, T A = +5C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Supply Currents VDD quiescent current I DDQ INL=INH= 5 µa VDD operating current I DDO fsw=5khz ma Floating driver quiescent current I BSTQ INL=INH= 6 9 µa Floating driver operating current I BSTO fsw=5khz. 3 ma Leakage Current I LK BST=SW=V.5 A Inputs INL/INH High.4 V INL/INH Low.4 V INL/INH internal pull-down resistance R IN 85 k Under Voltage Protection VDD rising threshold V DDR V VDD hysteresis V DDH.5 V (BST-SW) rising threshold V BSTR V (BST-SW) hysteresis V BSTH.55 V Bootstrap Diode Bootstrap diode ua V F.5 V Bootstrap diode ma V F.9 V Bootstrap diode dynamic R R ma.5 Low Side Gate Driver Low level output voltage V OLL I O =ma.5. V High level output voltage to rail V OHL I O =-ma.45.6 V Peak pull-up current I OHL V DRVL =V, V DD =V.5 A V DRVL =V, V DD =6V.5 A Peak pull-down current I OLL V DRVL =V DD =V.5 A V DRVL =V DD =6V 3.5 A Floating Gate Driver Low level output voltage V OLH I O =ma.5. V High level output voltage to rail V OHH I O =-ma.45.6 V Peak pull-up current I OHH V DRVH =V, V DD =V.5 A V DRVH =V, V DD =6V.5 A Peak pull-down current I OLH V DRVH =V DD =V.5 A V DRVH =V DD =6V 3.5 A MP8 Rev.. 3

4 ELECTRICAL CHARACTERISTICS (continued) V DD = V BST -V SW =V, V SS =V SW = V, No load at DRVH and DRVL, T A = +5C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Switching Spec. --- Low Side Gate Driver Turn-off propagation delay INL falling to DRVL falling T DLFF 6 ns Turn-on propagation delay INL rising to DRVL rising T DLRR 6 DRVL rise time C L =nf ns DRVL fall time C L =nf 9 ns Switching Spec. --- Floating Gate Driver Turn-off propagation delay INL falling to DRVH falling T DHFF 6 ns Turn-on propagation delay INL rising to DRVH rising T DHRR 6 ns DRVH rise time C L =nf ns DRVH fall time C L =nf 9 ns Switching Spec. --- Matching Floating driver turn-off to low side drive turn-on T MON 5 ns Low side driver turn-off to floating driver turn-on T MOFF 5 ns Minimum input pulse width that changes the output T PW 5 (5) ns Bootstrap diode turn-on or turnoff time T BS (5) ns Over Temperature Protection (5) OTP entry threshold 6 OTP recovery threshold 4 C OTP hysteresis Note: 5) Derived from bench characterization. Not tested in production. MP8 Rev.. 4

5 PIN FUNCTIONS Pin # Name Description VDD Supply input. This pin supplies power to all the internal circuitry. A decoupling capacitor to ground must be placed close to this pin to ensure stable and clean supply. BST Bootstrap. This is the positive power supply for the internal floating high-side MOSFET driver. Connect a bypass capacitor between this pin and SW pin. 3 DRVH Floating driver output. 4 SW Switching node. 5 INH Control signal input for the floating driver. 6 INL Control signal input for the low side driver. 7 VSS, Exposed Pad Chip ground. Connect to Exposed pad to VSS for proper thermal operation. 8 DRVL Low side driver output. MP8 Rev.. 5

6 TYPICAL PERFORMANCE CHARACTERISTICS V DD =V, V SS =V SW = V, T A = +5C, unless otherwise noted. I DDO (ma) I DDO Operation Current vs. Frequency T=-4 o C T= o C T=5 o C T=5 o C I BSTO (ma) 4 3 I BSTO Operation Current vs. Frequency T=5 o C T=5 o C T=-4 o C T= o C V OHL,V OHH (V) High Level Output Voltage vs.temperature V BST =V DD =9V V BST =V DD =V V BST =V DD =4V V OLL,V OLH (V) Low Level Output Voltage vs. Temperature V BST =V DD =9V V BST =V DD =V V BST =V DD =4V V BSTR,V DDR (V) Undervoltage Lockout Threshold vs.temperature V BSTR V DDR V BSTH,V DDH (mv) Undervoltage Lockout Hysteresis vs.temperature V DDH V BSTH T DHRR,T DLRR,T DHFF,T DLFF ( ns ) Propagation Delay vs. Temperature 9 T DHRR 8 7 T DLRR T DLFF 6 T DHFF I OHH,I OHL (A).5.5 Peak Pull-up Current vs. Output Voltage I OLH,I OLL (A) Peak Pull-down Current vs. Output Voltage V DRVH,V DRVL (V) V DRVH,V DRVL (V) MP8 Rev.. 6

7 TYPICAL PERFORMANCE CHARACTERISTICS (continued) V DD =V, V SS =V SW = V, T A = +5C, unless otherwise noted. Bootstrap Diode I-V Characteristics 4 Quiescent Current vs. Voltage Maximum V SW Voltage vs. V DD Voltage FORWARD CURRENT (A)... I DDQ,I BSTQ (ua) 8 6 I DDQ vs. V DD I BSTQ vs. V BST V SW TO V SS VOLTAGE (V) FORWARD VOLTAGE (V) V DD,V BST (V) V DD TO V SS VOLTAGE (V) Turn-on Propagation Delay Gate Drive Matching T MOFF Drive Rise Time (nf Load) 5V/div. 5V/div. Turn-off Propagation Delay Gate Drive Matching T MON Drive Fall Time (nf Load) 5V/div. 5V/div. MP8 Rev.. 7

8 BLOCK DIAGRAM BST VDD UNDER VOLTAGE LEVEL SHIFT DRVH DRIVER SW INH UNDER VOLTAGE DRVL INL DRIVER VSS Figure Function Block Diagram INL INPUT (INH, INL) INH T DHRR, T DLRR OUTPUT (DRVH, DRVL) T DHFF, T DLFF DRVL T MON T MOFF DRVH Figure Timing Diagram MP8 Rev.. 8

9 PACKAGE INFORMATION SOIC8 (EXPOSED PAD).89(4.8).97(5.) 8 5.4(3.5).36(3.45) PIN ID.5(3.8).57(4.).8(5.8).44(6.).89(.6).(.56) 4 TOP VIEW BOTTOM VIEW SEE DETAIL "A".3(.33).(.5).5(.3).67(.7) SEATING PLANE.(.).6(.5).5(.7) BSC SIDE VIEW.75(.9).98(.5) FRONT VIEW.(.5).(.5) x 45o GAUGE PLANE.(.5) BSC.4(.6).63(.6).5(.7) o -8 o.6(.4).5(.7) DETAIL "A".38(3.5).3(.6) RECOMMENDED LAND PATTERN.3(5.4) NOTE: ) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. ) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.4" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-, VARIATION BA. 6) DRAWING IS NOT TO SCALE. MP8 Rev.. 9

10 QFN8 (3mm 3mm) PIN ID MARKING PIN ID SEE DETAIL A PIN ID INDEX AREA BSC TOP VIEW BOTTOM VIEW. REF.8. PIN ID OPTION A.3x45º TYP. PIN ID OPTION B R. TYP...5 SIDE VIEW DETAIL A.9 NOTE: ) ALL DIMENSIONS ARE IN MILLIMETERS. ) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE. MILLIMETER MAX. 4) DRAWING CONFORMS TO JEDEC MO-9, VARIATION VEEC-. 5) DRAWING IS NOT TO SCALE RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP8 Rev..