managed by Brookhaven Science Associates for the U.S. Department of Energy VMM1 Front-end ASIC for charge-interpolating micro-pattern gas detectors

Transcription

1 managed by Brookhaven Science Associates for the U.S. Department of Energy VMM1 Front-end ASIC for charge-interpolating micro-pattern gas detectors Gianluigi De Geronimo Instrumentation Division, BNL April 2012

2 Targeted architecture Neighbor enable (channel or chip) Trigger in Clock (10MHz) ART ART (rejects data if no trigger after X counts) coarse time 100ns tstop trigger identifier 4-bit counter input charge range 0.11, 0.33, 1.0, 2.0 pc CA capacitance 1pF-400pF SA peaktime 25,50,100,200ns DSC PD/TD time tstart amplitude 6-bit counter enable stop at 1 st cnt TAC fine time 1.5ns TADC 6-bit amplitude AADC 10-bit FIFO 32-bit x N channel address ADDR 6-bit 200ns conv. 64 channels, adj. polarity, adj. gain (0.11 to 2 pc), adj. peaktime ( ns) note: interest in 5 pc peak detection (10-bit) and time detection (1.5 ns) real-time first address sub-threshold neighbor acquisition (channel or chip) 10-bit single-trigger ADCs derandomizing buffer for continuous operation integrated threshold and pulse generators monitors, channel mask, temperature sensor, 600mV-LVDS interface ~ 5 mw per channel, CMOS 130 nm 2

3 Initial architecture ( first prototype ) Neighbor enable (channel or chip) ToT/TtP Trigger in Clock (10MHz) ART ART (rejects data if no trigger after X counts) coarse time 100ns tstop trigger identifier 4-bit counter input charge range 0.11, 0.33, 1.0, 2.0 pc CA capacitance 1pF-400pF SA peaktime 25,50,100,200ns DSC PD/TD Tlog time tstart amplitude 6-bit counter enable stop at 1 st cnt TAC fine time 1.5ns TADC 6-bit amplitude AADC 10-bit MUX channel address ADDR 6-bit 200ns conv. 64 channels, integrates almost all of the critical functions MUX replaces ADCs and FIFO external trigger replaces TAC stop ADC architecture being in a separate project includes direct ToT (time-over-threshold) or TtP (time-to-peak) on 16 channels (0-7 and 56-63) note: interest in PdT (peak-discharge-to-threshold) 3

4 Operation and functions BGR - bias - temperature pulser - threshold registers CA 64 channels SA Modes of operation neighbors trigger (channel or chip) PD/TD en wen ck tki di ART DSC logic acquisition enable tstart tstop TAC 6-bit time ampl addr TOT MUX ch 0-7,56-63 flag time ampl acquisition: events are detected and processed (amplitude and timing) charge amplification, discrimination, peak- and time-detection address in real time (ART) of the first event direct timing (ToT or TtP) per channel for channels 0-7 and readout: sparse mode with smart token passing (amplitude, timing, addr.) configuration: access to global and channel registers addr Functions common temperature monitor pulse generator (10-bit adjustable amplitude) coarse threshold (10-bit adjustable) self-reset option analog monitors analog, trim thresholds, BGR, DACs, temp. analog buffers analog section charge amplifier (200pF), high-order DDF shaper adjustable polarity (negative, positive) gain: 0.5, 1, 3, 9 mv/fc (2, 1, 0.33, 0.11 pc) peaktime: 25, 50, 100, 200 ns test capacitor 1.2pF, channel mask discriminator trimmer (4-bit adjustable, 1mV) sub-hysteresis pulse processing option neighbor logic on channels and chips (ch0, ch63) peak detector multiphase time detector TAC ramp (selectable 100, 200, 500, 1000 ns) start at peak-found stop selectable (ena-low or stp-low) ART address of the first event in real time selectable at first threshold or at first peak self-resets in 40ns fflag indicates event address available at fa0-fa5 timing per channel available for channels 0-7 and selectable between ToT and TtP readout flag at first peak indicates events to readout sparse with smart token passing (skips empty chan.) amplitude available at pdo timing available at tdo address available at a0-a5 4

5 Channel monitor trim discrim. ART neigh token analog PD TD regist. size 4.7 mm x 100 µm power dissipation ~ 4mW at 25 ns peaktime 5

6 Analog section baseline stabilizer charge amplifier polarity DDF shaper charge amplifier two stages, continuous reset, adjustable gain: 0.5, 1, 3, 9 mv/fc (2, 1, 0.33, 011 pc) optimized for C DET = 200 pf, can operate with C DET = 1pF - 400pF input MOSFET: NMOS W/L 10mm/180nm, I D 1.65mA, P D 2mW, C G 18pF, g m 38mS shaper 3 dr order, complex-conjugate poles, delayed-dissipative feedback (DDF) adjustable peaking time: 25, 50, 100, 200 ns baseline stabilizer (BLH) 6

7 Amplitude [V] ENC (e - ) Analog section - simulations 1/2 Charge Resolution 5k Q max = 330 fc peaktime 25ns 50ns 100ns 200ns 0 0 C IN [pf] Pulse Response Q in = 300 fc Target resolution < 5,000 e - at 200 pf, 25 ns 0 0 time [ns] 150 7

8 Analog section - simulations 2/2 without and with RC parasitics shaper output adjustable gain charge amplifier output Q=100fC Q=800fC, G=1mV/fC, C DET =200pF adjustable peaktime adjustable polarity Q=800fC Q=800fC 8

9 Discriminator Discriminator and ART hyst. ctrl loop comparator size 130 µm x 70 µm comparator hysteresis (positive feedback) ~ 20mV comparator response ~ 1ns hysteresis control loop reduces effective hysteresis to 1 mv can detect events down to 2 mv (signal dynamic range ~ 500) ART fast OR node size 50 µm x 25 µm ART (Address in Real Time) provides address first event uses fast OR, multiplexed twice (x 8 and x 8) response 2 ns within 2 ns, lowest order channel wins 9

10 Peak and time detectors - simulations without and with RC parasitics pdo threshold pulse tdo ramp threshold peak found token reset TAC stop signal at 150ns (not visible); timing at peak found (low time walk) 10

11 Readout - simulations 1/2 wen ena rst ck pulser ck timing ck (for counter) readout ck internal enable token input ART flag ART address flag address threshold PDO ART at threshold (selectable), flag at peak 11

12 Readout - simulations 2/2 wen ena rst ck pulser ck timing ck readout ck internal enable token input ART flag ART address flag address threshold PDO channels 2, 4, 6, 10, 12, 14 exceed threshold; neighbors are collected channel 45 hits 2 ns earlier than others (ART) 12

13 Registers Common bits sg0,sg1: gain (0.5, 1, 3, 9 mv/fc)(2, 1, 0.33, 0.11 pc) st0,st1: peaktime (25, 50, 100, 200 ns) sng: neighbor (channel and chip) triggering enable stc0,stc1: TAC slope (125, 250, 500, 1000 ns) sdp: disable-at-peak scmx, sm0-sm5: monitor multiplexing sfa, sfam: ART enable and mode (peak, threshold) sbfm,sbfp,sbft: buffers enable (mo, pdo, tdo) sstp: TAC stop setting (ena-low or stp-low) ssh: sub-hysteresis discrimination enable sttt,stot: timing outputs enable and mode (ToT or TtP) s16: makes ch 7 neighbor to ch 56 srst: self reset enable (40ns after flag) sdt0-sdt9: coarse threshold DAC sdp0-sdp9: test pulse DAC Channel bits sp: charge polarity sc: large input capacitance mode (C DET >30pF) sl: leakage generator enable st: test capacitor enable sm: mask enable sd0-sd3: trim threshold DAC smx: mux monitor mode (analog or trim threshold) 13

14 64 inputs Core bias, BGR, temp. sensor control logic common registers 64 channels monitor pdo tdo addr buffers threshold DAC pulser pulser DAC size 4.7 mm x 7.1 mm five banks of MOSCAP filters on bias lines power dissipation ~ 300 mw 14

15 Top level LVDS IOs CORE size 5.9 mm x 8.4 mm 15

16 Pinout Pinout 176 pins (44 each side) Vdd,Vss: analog supplies 1.2V and grounds 0V Vddd, Vssd: digital supplies 1.2V and grounds 0V Vddp0-Vddp3: charge amplifier supplies 1.2V V600m: reference for LVDS 600mV BGR - bias - temperature pulser - threshold registers CA 64 channels neighbors trigger (channel or chip) SA PD/TD en wen ck tki di ART DSC logic acquisition enable tstart tstop TAC 6-bit time ampl addr TOT MUX ch 0-7,56-63 flag time ampl addr i0-i63: analog inputs, ESD protected mo: monitor multiplexed analog output pdo: peak detector multiplexed analog output tdo: time detector multiplexed analog output flag: event indicator a0-a5: multiplexed address, tristated (driven with token) ttp0-ttp7 and ttp56-ttp63: ToT or TtP fflag: ART event indicator fa0-fa5: ART address output stp: timing stop sett, setb: ch0, ch63 neighbor chip triggers (bi-directional) ena: acquisition enable ena high, wen low: acquisition mode ena low, wen low: readout mode ena pulse, wen high: global reset wen: configuration enable wen high: configuration mode wen pulse: acquisition reset ck: clock in acquisition mode ck is counter clock in readout mode ck is readout clock in configuration mode ck is writein clock tki, tko: token input and output (3/2 clock wider) di, do: data configuration input and output (1/2 clock shifted) in acquisition mode di is pulser clock 16

17 Schedule and status scheduled completed Analog section Jan 2011 February 2011 Peak/time section March April Common circuitry April May Digital sections May July Physical layout July October Fabrication September Queued for November 7th technology IBM 8RF CMOS 130 nm size 5.9 mm x 8.4 mm (~50mm²) pads count 176, package LQFP 176? 17

18 Schedule and status: update March 2012 Packaged in LQFP208 (instead of LQFP 176) Received from MOSIS 3/7/2012 Test board fabricated 3/22/2012 Test board assembled 3/29/2012 DAQ development in progress 18

19 Status as of April 2 nd, Test Board 19

20 Status as of April 2 nd, Test Board 20

21 Status as of April 2 nd, Test System 21

22 Status as of April 2 nd, Interface 22

23 Preliminary results as of April 2 nd, Pulse Response Input charge ~90 fc pktime 25, 50, 100, 200 ns Input charge ~90 fc gain 0.5, 1, 3, 9 mv/fc Measured output noise at 9mV/fC peaktime outnoise enc 25, 50, 100, 200 ns 0.49, 0.81, 1.16, 1.52 mv 340, 560, 800,

24 Preliminary results as of April 2 nd, Peak Detection EN PDO FL CK FL PDO 24

25 Preliminary results as of April 2 nd, Timing Detection CK FL TDO ramp 125ns CK FL TDO ramp 1us 25

26 Preliminary results as of April 2 nd, Neighboring CK FL neigh chip PDO neigh channel 26

27 Preliminary results as of April 2 nd, Fast Flag ART at threshold FL ART at peak FL 27

28 Preliminary results as of April 2 nd, Timing Outputs 1/2 ART at peak FL ART at peak FL ToT TtP 28

29 Preliminary results as of April 2 nd, Timing Outputs 2/2 ART at peak FL ART at peak FL ToT TtP 29

30 Preliminary results as of April 2 nd, Summary Most relevant issues so far: large leakage from input protection increases noise (~400e - ) and disables positive charge front-end circuit (needs external current compensation, e.g. resistor) self-reset function does not reset discriminator analog pulse shows some digital pick-up mixed signal issues to be investigated 30

31 Backup slides 31

32 Integrated output noise spectral density [µv rms] Output [mv] Delayed dissipative feedback (DDF) Classical 25k 67k 12 C f - 106xC f p 21k 16k 3.1p - V o 10 8 Input charge 1 fc CU3 CU3 DDF same range, ~30% area CU3 DDF same area, ~2x range charge amplifier shaper 19p 6 DDF equal DR 300k 700f 4 2 C f - charge amplifier DDF equal C 28xC f 2.9p - 78k 84k 98k 2.2p - shaper 38k 2.9p 41k 2.9p - V o CU3 Time [µs] CU3 DDF same range, ~30% area CU3 DDF same area, ~2x range C f 11.2p 25k 8.5p 11k 11.2p xC f - 22k - 10k - V o 40 charge amplifier shaper 20 G. De Geronimo et al., IEEE TNS 58 (2011) Frequency [Hz] 32

33 Peak detector - classical configuration V TH - + peak-found V i - + G d V g V DD M h V hp V h i h C h s h detects and holds peak without external trigger provides accurate timing signal (peak found, z-cross on derivative) low accuracy (op-amp offset, CMRR) poor drive capability 33

34 Peak detector - multiphase in _ + M P 1 - Track (< threshold) Analog output is tracked at hold capacitor M P and M N are both enabled C H M N peak-found 2 - Peak-detect (> threshold) Pulse is tracked and peak is held Only M P is enabled Comparator is used as peak-found in _ + M P out C H V P M N _ + C H V P M P M N 3 - Read (at peak-found) Amplifier re-configured as buffer High drive capability Amplifier offsets is canceled Enables rail-to-rail operation Accurate timing Some pile-up rejection 34

35 Signal [V] Signal [V] Peak detector - multiphase Chip 1 negative offset Chip 2 positive offset gate ( peak-found, timing ) gate ( peak-found, timing ) out hold 0.6 hold out in 0.2 in Time [µs] Time [µs] 35

36 amplitude amplitude Peak detector - timing function Compare timing at threshold crossing with timing at peak ENABLE Threshold crossing Peak detection TAC RAMP TDO TAC RAMP TDO 0 0 V A V TH 0 t 0 t C t t CTH CS time 0 t 0 t A V APK t APK t CS time t Q ENC ds output slope normalized to unit charge t ENC p Q p p Time-walk strongly dependent on amplitude Time-walk almost independent of amplitude (equivalent to zero crossing on differential) 36

37 Timing resolution t (ns) Time walk (ns) Peak detector - timing function Compare timing at threshold crossing with timing at peak 100 Peaking time 1µs Energy resolution 200 e Threshold Crossing (0.5% of max) Peaking Time Injected Charge (fc) t ENC p Q p p 37

38 Shaper coefficients for amplitude and timing resolution Filter Shape a w a ƒ (1) a p ƒ ( ƒ )=a ƒ ( ƒ )/a ƒ (1) w / p - p p p 1 RU RU RU nd RU-5 nd th 7 RU-6 th RU CU CU CU nd CU-5 2 nd CU-6 7 th CU RB RB RB-4 nd nd RB th 7 RB th RB CB CB nd 2 CB nd CB CB-6 th th CB