HINP4 Progress Report

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Janel Wiggins
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1 HINP4 Progress Report George Engel, D.Sc. Srikanth Thota (student) IC Design Research Laboratory Department of Electrical and Computer Engineering Southern Illinois University Edwardsville, IL, Design Status February

2 Energy Branch Block Diagram IC Design Research Laboratory

3 CFD Block Diagram CSA signal comes from first op amp in the slow shaper of the high gain branch in previous slide. Digital delay block in zero-cross leg compensates for delay through x10 amplifier.

4 Performance Characterization Linearity of Energy Branch (input-to-output) Shaper Response (peaking time) Energy Resolution as Function of Detector Capacitance Minimum CFD Trigger Level as Function of Detector Capacitance CFD Walk Performance as Function of Energy

5 Linearity of Energy Branch Linearity limited by the charge amplifier. Linearity of shaper, peak detectors, and off-chip driver quite good. Linearity plots which follow are for charge amp input to off-chip differential driver output Complete electrical simulation.

6 Differential Output (Volts) Difference (MeV) Differential Output (Volts) Difference (MeV) Linearity Plots (Electron Collection) IC Design Research Laboratory 0 Electron Collection Linearity Plot (Low Gain) Electron Collection Differential Plot (Low Gain) Energy (MeV) 0-1 Energy (MeV) Electron Collection Linearity Plot (High Gain) 3 2 Electron Collection Differential Plot (High Gain) Energy (MeV) Energy (MeV) 6

7 Differential Output (Volts) Difference (MeV) Differential Output (Volts) Difference (MeV) IC Design Research Laboratory Linearity Plots (Hole Collection) Hole Collection Linearity Plot (Low Gain) Hole Collection Difference Plot (Low Gain) Energy (MeV) Energy (MeV) Hole Collection Linearity Plot (High Gain) Hole Collection Difference Plot (High Gain) Energy(MeV) Energy (MeV) 7

High Gain Mode Shaper Output for Electron Collection with Energy level: 10MeV : (Cdet : 75pF) Settling Time:5 µs NOTE the excellent return to baseline characteristics

High Gain Mode Shaper Output for Hole Collection with Energy level: 10MeV: (Cdet : 75pF) Settling Time: 50µS NOTE that it takes much longer to return to baseline

8 High Gain Mode Shaper Output for Electron Collection with Energy level: 10MeV : (Cdet : 75pF) Settling Time:5 µs NOTE the excellent return to baseline characteristics when the dynamic reset circuit is used. Peaking time is 1.5 usec. High Gain Mode Shaper Output for Hole Collection with Energy level: 10MeV: (Cdet : 75pF) Settling Time: 50µS NOTE that it takes much longer to return to baseline because of the real feedback resistor. Current shaper has no way to cancel the pole which is introduced by the feedback resistor. The novel reset circuit used above cannot be used because of the poor 1/f noise performance of NFETs in this process. Peaking time is 1.5 usec. 8

9 Energy Resolution We have used a detector model where the leakage current is assumed to be 100 na (aging detector) Noise bandwidth for noise analysis was 1 mhz to 5 MHz. Simulations were run to see whether noise would increase as function of energy level when collecting electrons because of the novel reset circuit. The answer is NO significant increase in noise level could be observed with increased energy levels. The noise from the peak detectors and off-chip driver is not currently included. They must be simulated separately (not easy) but since they use correlated double sampling (CDS)to reduce the 1/f noise contribution we expect it to be excellent.

10 Resolution (KeV) Resolution (KeV) IC Design Research Laboratory Energy Resolution 80 Energy Resolution (Electron Collection) 80 Eneregy Resolution (Hole Collection) ' 60 ' High_Gain Low_Gain Detector Capacitance (pf) High_Gain Low_Gain Detector Capacitance (pf) 10

11 Minimum Trigger Level of CFD Minimum trigger level set so that threshold is 6 times the RMS noise level at input to leading-edge circuit and LE signal must fire before ZC signal. Detector Capacitance Minumum Trigger Level (Electron Collection) Minumum Trigger Level (Hole Collection) 25 pf 125 kev 115 kev 75 pf 190 kev 180 kev 150 pf 350 kev 340 kev 300 pf 730 kev 690 kev

12 ZC_time(ns) IC Design Research Laboratory CFD Walk Performance (Electron Collection) ZC_time Vs Energy (Electron Collection ) 40pF 75pF 150pF Energy(MeV)

13 ZC_time(ns) IC Design Research Laboratory CFD Walk Performance (Hole Collection) ZC_time Vs Energy ( Hole Collection ) 40pF 75pF 150pF Energy(MeV)

14 Reasons for Delay in Fabbing Chip IC Design Research Laboratory As we pushed for greater resolution and higher dynamic range the poor 1/f noise performance of the NFETs in the process we are using became a larger impediment. We were forced to completely re-design the peak detect circuits as well as the off-chip driver. In HINP3 we came off in a single-ended fashion and now we are differential. A switched-capacitor circuit capable of canceling 1/f noise is used. The reset circuits required by the charge amplifier were not easy to design, once again in large part due to the poor 1/f noise performance of the NFETs in this process. A low-level oscillation during large transients was a tough problem to track down and solve. Reducing the minimum trigger level of the CFD turned out to be a much more difficult problem than we had anticipated. We are a very small group: 1 professor and two (now four) grad students.

15 Work still left to complete Odd behavior displayed in walk characteristic requires further investigation. Differential output driver layout started but much more needs to be done before the layout is complete. Noise analysis needs to be performed (not simple). As accurate model of off-chip ADC is needed so we can be sure that we won t have stability issues when driving the ADC input. Peak detectors need further characterization (especially noise performance) and then peak detector circuitry needs to be layed out and integrated into the HINP4 s energy branch layout. This involves a significant effort. Charge amplifier, CSA, and shaper layouts are now complete! Layout of energy branch from HINP3 needs to be removed and replaced with HINP4 layout for energy branch.

16 Work still left to complete (continued) Changes have to be made to the CFD layout to accommodate some of the changes we made to the design. We need to design, simulate, and layout digital control logic associated with the switched-capacitor single-to-differential output driver and integrate into readout electronics. A similar effort needs to be expended to produce the reset, read, and write signals required by the new peak detector circuits. More thought has to be given to making sure the IC is testable. The correct operation of entire chip needs to be verified using Verilog-AMS simulator. A single run just to readout a few values will require several days of simulation In short, we are still a long way from being able to fabricate a chip that has any chance of working!

Low noise Amplifier, simulated and measured.

Low noise Amplifier, simulated and measured. Introduction: As a study project a low noise amplifier shaper for capacitive detectors in AMS 0.6 µm technology is designed and realised. The goal was to design