Development of a Multi-Channel Integrated Circuit for Use in Nuclear Physics Experiments Where Particle Identification is Important

Transcription

1 Development of a Multi-Channel Integrated Circuit for Use in Nuclear Physics Experiments Where Particle Identification is Important Michael Hall Southern Illinois University Edwardsville IC Design Research Laboratory April 3, 2007

2 Design Team Southern Illinois University Edwardsville: Dr. George Engel (PI) Michael Hall (graduate student) Justin Proctor (graduate student) Venkata Tirumasaletty (graduate student) Washington University in St. Louis: Dr. Lee Sobotka (Co-PI) Jon Elson (electronics specialist) Dr. Robert Charity Western Michigan: Dr. Mike Famiano (Co-PI) 2

3 Research Objective Design a custom microchip which can be used by nuclear physicists when they perform experiments. In these experiments, physicists use detectors to sense radiation. These experiments often require that the physicists identify the type of radiation (α( particle, γ-ray, etc) that struck the detector. 3

4 NSF Proposal (Funded) $200,000 grant funded from September 2006 to August Design, simulate, and fabricate a custom integrated circuit for particle identification suitable for use with CsI(Tl) (used for charge-particle discrimination) Liquid Scintillator (used for neutron-gamma discrimination) 8 channel prototype chip 16 channel production chip 4

5 Intended Applications The chip will be used in an experiment at the National Superconducting Cyclotron Laboratory (NSCL) in Fall 2007 by Washington University collaborators. Mass production of PSD technology is actively being sought by our government s Department of Homeland Security. 5

6 Chip and Sensor Array HiRA Detector Array at MSU Earlier IC developed in our lab currently being used in Physics experiments around the country 6

7 Simulated Input Pulse for CsI(Tl) Detector Input Pulses (V) Integrators A 0 to 400 ns B 1500 to 1500 ns C 0 to 9000 ns Integration periods at the beginning of the signal are assumed to start before the pulse (at -55 ns). 7

8 Need for an Integrated Circuit Particle identification (α( particle, γ-ray, etc.) capability Ability to support multiple (i.e.( initially eight but eventually sixteen) radiation detectors Three separate integration regions with independent control of charging rate in each region which can be used for high-quality pulse shape discrimination (PSD). Built-in in high-quality timing circuitry Multiple (3) triggering modes Data sparsification 8

9 Overview of PSD System OR A VME C F D Exte rna l logic V(t) [current through a load R] C B Detector Gate control WA WB WC DA DB DC PSD Integrator Chip A B C T Sa m ple Integration gates D E L A Y Multiplexed with other chips and sent to 4 channels of one VME Pipeline ADC Cable Detector (PMT or photodiode) External discriminators (CFDs) External delay lines so we can start integrations before arrival of pulse External control voltages determine Delay and Width of integration periods Outputs A, B, C integrator voltages and relative time, T 9

10 Channel 3 on-chip sub- channels for integrators A, B, C Delay and width of integrators set by externally supplied control voltages Timing relative to a common stop signal 10

11 Sub-Channel t 0 Event StartInt StopInt DUMP INT-x t 1 t 2 t 4 t 3 t 5 StartInt DUMP Event Delay Generator Start Out Delay Generator Start Out StopInt INT-x Dx Control Wx Control DUMP Input from Detector Resistor Array INT-x 10 pf Where X = A, B, C 3 DAC Setting DAC Control Out OPAMP Integrator Output AGND SUB CHANNEL 11

12 Pulse Shape Discrimination Plot for CsI(Tl) Detector Integrator B (mv) PSD (Pulse Shape Discrimination) Plot Alpha Proton Integrator A (mv) Detector: CsI(Tl) Integrators: A, B Energy Max: 100 MeV (for 2V at input of integrator) Energy Range: MeV Includes all noise sources 12

13 Angular PSD Plots (CsI) Energy = 1 MeV, Perr = 2.16% Energy = 10 MeV, Perr = 0% Alpha Proton Count Count Theta Theta Count Energy = 100 MeV, Perr = 0% Theta Detector: CsI(Tl) Integrators: A, B Energy Max: 100 MeV Energy Range: MeV 5000 realizations Includes all noise sources 13

14 Current Work Circuit design and simulations Behavioral level simulations (VerilogA) to verify functionality of one complete channel including read-out electronics 14

15 Future Work Layout Fabrication Chip should leave for fabrication in August Will take approximately 2 months to make. Testing of the IC Chip will be used in experiment at NSCL in Fall