Analog Peak Detector and Derandomizer

Transcription

1 Analog Peak Detector and Derandomizer G. De Geronimo, A. Kandasamy, P. O Connor Brookhaven National Laboratory IEEE Nuclear Sciences Symposium, San Diego November 7, 2001

2 Multichannel Readout Alternatives Direct digitization Track-and-Hold + Analog Multiplex Analog Memory + Analog Multiplex P/S P/S ANLG MUX P/S ANLG MUX ADC T/H ADC T/H ADC... ADC CK CK ADC T/H CK SAMPLE CELL ADDR most flexible requires many fast ADCs expensive, high power requires trigger has deadtime timing uncertainty requires sparsification requires trigger can be deadtimeless (complex control) requires sparsification

3 Ideal Self-triggered, Self-sparsifying, Deadtimeless Readout S3 P/S S1 S2 S4 S5 CH 1 PK HT ADC CH 2 READ REQ... CH 3 ADDR A1 A2 A3 A4 A5... DAQ CH N PK TIME T1 T2 T3 T4 T5

4 Peak Detector (PD) Advantages self-triggering self-sparsifying timing output in + - peak held out reset C H Drawbacks accuracy impaired by op-amp offsets, CMRR, slew rate poor drive capability deadtime until reset

5 Improved CMOS PD Using Two-Phase Configuration Write phase conventional peak detector M1: unidirectional current source voltage on C H includes op-amp errors (offset, CMRR) in - + v off C H out M1 Read phase out same op-amp re-used as unity-gain buffer same CM voltage in - + v off M1 op-amp errors cancel enables rail-to-rail sensing C H provides good drive capability

6 Two-Phase Peak Detector in 0.35 µm CMOS PD loop with switches SCHEMATIC LAYOUT 340 µm 50 µm Switch control logic (data driven) reset RST D Q R 245 µm Vg Vref + - V CK QB W 50 µm

7 Two-Phase CMOS Peak Detector - Results Waveforms Absolute accuracy V g / V DD Signal [V] V h V o V i V ip Error in peak height (mv) us 0.5 us 5 us 15 us Time [µs] (b) Peak Amplitude (V) Droop rate Time walk V o 36 Tp=500ns Signal [V] Delay (ns) Tp=200ns ± 2.3ns Time [s] Peak amplitude (V)

8 Two-Phase CMOS Peak Detector - Summary Self-triggering 2-phase operation eliminates op-amp errors High absolute accuracy independent of process, supply, temperature variation Rail-to-rail input and output Strong drive capability No switch charge injection into hold node Timing output Parameter Technology Supply voltage Input voltage range Absolute accuracy Time walk Value 0.35 µm CMOS DP4M 3.3 V V 0.2 %, t p 500ns 0.7%, t p =200ns ± 2.3 ns, V in < 2.5 V ± 5 ns, V in < 3 V Droop rate 0.25 V/s Power dissipation 3.5 mw Cell area 0.03 mm 2

9 Peak Detector and Derandomizer Combine the peak detect and analog hold functions of the PD with additional analog storage and control logic to create a Peak Detector Derandomizer (PDD). PDD behaves like a data driven, analog FIFO memory. Topologies: 2Φ PD IN OUT RST PK 2Φ PD V IN 2Φ PD IN OUT RST PK SCA (ANALOG BUFFER) V OUT V IN 2Φ PD OUT IN Vh RST PK V OUT SCA (MULTIPLE HOLD CAPS) IN RST OUT PK HIT RST CONTROL CAP ADDR RD REQ RESET V IN 2Φ PD IN OUT RST PK VOUT B: PD plus SCA as analog buffer HIT RST CONTROL CAP ADDR C: PD with multiple hold capacitors RD REQ RESET Sin CONTROL HIT Sout A: Array of PD with ping-pong control RD REQ RESET Topology A with two parallel PDs has been fabricated and tested.

10 Multichannel Readout System with PDD PULSER SOURCE 16 P/S 16 READ RST CNVT CZT ARRAY 32 SSM PDD ADC PK FND P/S 16 ADDR 5 PEAK LOGIC ANAL. SSM: self-switched multiplexer; custom chip that detects above-threshold inputs and routes them to PDD input. In response to a READ request from the DAQ system (pulser), the next peak sample stored in the PDD is presented to the 12-bit ADC. After a fixed delay the pulser RESETs the PDD that was read out, freeing it to process next input pulse.

11 Multichannel PDD Readout System: First Results READ PDD OUT PDD IN PK FND Input pulses from source occur randomly READ process is synchronous 200 khz READ rate matches average input rate Simultaneous readout and acquisition of new data 2-sample buffer absorbs rate fluctuations Time, us

12 Multichannel PDD Readout System FWHM 4.2 kev Kcounts Energy (kev) Spectra Solid line: commercial MCA. Points: PDD, single channel. Circles: PDD, 16 channels gain-adjusted. Resolution limited by CZT detectors Source Profile Channel No. 241 Am source centered over channel 2.

13 Summary New 2-phase peak detector in submicron CMOS: High absolute accuracy (0.2%) and linearity (0.05%) Rail-to-rail input and output ± 2.3 ns time walk Low power (3.5 mw) Extremely compact (0.03 mm 2 ) A building block for compact, efficient multichannel readout system: Self-triggered Self-sparsifying Deadtimeless Peak detector derandomizer (PDD) with 2-event buffer demonstrated: First step towards data-driven analog FIFO readout