High Speed Analog CMOS Pipeline System for the Recording of Fast Signals from Cherenkov Telescopes

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1 High Speed Analog COS Pipeline System for the Recording of Fast Signals from Cherenkov Telescopes CRISTIAN CHIŢU ; and WERNER HOFANN ASIC Labor Universität Heidelberg Schröderstr.90, D-690Heidelberg ax-planck-institut für Kernphysik Saupfercheckweg, D-69 Heidelberg GERANY Abstract: - Analog sampling systems based on switched capacitor techniques offer performance superior to that of flash A/D converters with respect to cost, density, dynamic range, sampling speed, and power consumption. This paper proposes a 500 Hz switched capacitor analog waveform sampling circuit for the camera electronics of the Cherenkov telescope. An experimental channel analog memory with 8 sampling cells in each channel has been integrated in a 0.8 m COS technology with poly-to-poly capacitors. The acquisition time of the analog memory is less than 0.5 ns and the readout sampling rate is 00 khz. The circuit and chip concept are presented, together with some design optimisations. Key-Words: - switched capacitor, bandwidth, servo feedback, delay chain, memory cell, analog memory, sampling capacitor, switch. Introduction Analog switched capacitor memory circuits are suitable for use in a wide range of applications where analog waveforms must be captured or delayed, such as the recording of pulse echo events and pulse shapes. In a number of applications such as the Cherenkov application [3] analog waveforms need only be captured as snap shots and continuous digitisation is not necessary. The electrical signal generated in the photomultiplier detector (PT) of the Cherenkov telescope is amplified and the input waveform is sampled at a high rate for a limited period of time, and the samples are stored in the analog memory. The analog samples are then retrieved at a lower rate and digitised with a slow analog-to-digital (ADC) converter before a new waveform is acquired. Advantages of using an analog memory in the camera electronics of the Cherenkov telescope include low overall power dissipation and cost, high density, and potentially superior dynamic range at high sampling rates. The proposed analog memory circuit is described in detail in Section of this paper. In Section 3 the design of the on-chip write and read control circuitry is explained. The implementation of the circuit is presented in Section. Analog emory Description In Fig. is shown a block diagram of the FASTSAP- (F ast Sampling Transmission Recorder - First ersion) chip with memory channels. The analog waveforms applied at the inputs are sampled and stored in the analog memory core. The write and read addresses for the core are generated in the write and read control blocks, respectively. Since all memory channels are written and read simultaneously, the addresses are common to all channels. The other signals which appear in the block diagram are provided externally. A simplified schematic [] of one channel of the proposed analog memory, comprising blocks of 3 cells, is shown in Fig.. Each memory cell consists of a large write transistor wi, a minimum size read transistor ri, and a sampling capacitor C i. The cells are addressed via write lines w < >

2 Phi Phi Phi3 Phi Read Control Circuit In In In3 In ComInOut ComReset Write Control Circuit w<>...w<8> Aref Aref Aref3 Aref in ComIn in 00 r<> r<> input bus r<8> ComOut 00 out AnalogInputCh AnalogInputCh x 3 Cell emory Channel x 3 Cell emory Channel AnalogOutputCh AnalogOutputCh C C C 8 AnalogInputCh3 AnalogInputCh x 3 Cell emory Channel x 3 Cell emory Channel r<>...r<8> AnalogOutputCh3 AnalogOutputCh w r w r read bus 00 w8 r8 B o ComReset Phien Read Control Circuit Address6...Address0 C reset Fig.. Block diagram of the FASTSAP- chip. through w<8 > and read lines r< >through r < 8 >. The voltage C is a dc reference common to the sources of all write transistors, wi.the switch reset serves to configure the operational amplifier as a voltage follower in order to force the nodes of the amplifier input and output to the dc bias level B during reset. The operation of the circuit can be described into write and read cycles. In the write phase, analog signals applied at the channel input, in, are sampled and stored in the memory cells at a high rate. The stored analog information is subsequently read out serially at the channel output, o, at a lower speed. During the write phase, the switch in is turned on, connecting the signal in to the input bus, while the switch out and the read switches r through r8 are all off, isolating the input bus from the read bus. The switch reset is on to keep the read bus at a defined potential, B, during the entire write phase. An analog signal applied at the circuit s input is sampled onto the cell capacitors C i by sequentially turning transistors w through w8 on and off, as illustrated in Fig. 3(a). Samples of the input waveform at 8 discrete times are thereby stored in the memory channel. The voltage si stored across the capacitor C i in the memory cell i, i 8, is after the sampling si = in, C, pwi () where pwi is the voltage error due to the charge injection in the switch wi during turn off [5]-[6]. The source and drain terminals of the write transistor are at the reference voltage C at turn off. The voltage pwi [5]-[6] can be written as w<> w<> 00 Write Control Circuit w<8> Fig.. Simplified schematic of one analog memory channel. pwi =, C wi + C oxw wil wi erf, s C tot s UC tot UC tot ( H, C, T ) C wi C wi + C pi + C i ( C, L + T ) () where C wi is the write transistor gate overlap capacitance, C i is the sampling capacitance, T is the threshold voltage, L and H are the low and high levels of the write transistor gate voltage, C ox is the oxide capacitance per unit area, W wi and L wi are the width and length of the write transistor, U is the slew rate of the gate voltage, C pi is the capacitance associated with the cell sampling capacitor terminal connected to the write switch wi, = n C ox W wi =L wi,and n is the electron mobility in the channel. The capacitance C tot is C tot = C i + C pi + C wi + C oxw wi L wi : (3) The important fact of this investigation is that pwi remains independent of the input voltage, in. After the write phase has been completed and the input waveform is stored in the analog memory, the read cycle is initiated. During the readout, the switch in is turned off while out and reset are turned on,!,

3 (a) in ComIn w<> w<> w<8> ComOut ariable Simulation Open-loop gain 98 db -3dB bandwidth 5 Hz Unity-gain bandwidth.9 Hz Integral linearity 0.03 % Slew-rate 3.83 /s Equivalent input referred f=00 khz 33 n/ Hz Table. Simulation results at 0 pf load capacitance. (b) ComReset r<> r<> r<8> o Fig. 3. Timing diagram for the (a) write and (b) read phases. forcing both the input bus and the read bus to B.The switch reset is then turned off and the voltage stored in the first cell is read out by turning r on, as illustrated in Fig. 3(b). This cycle is repeated for all cells. The input bus must always be forced back to B before a new cell is read out, otherwise the charge and parasitic capacitances will seriously degrade the circuit s performance. By turning the cell read switches off after the reset switch is turned on, the potential across the capacitors is initialised to nominally 0 for the next write phase. Once the write switch is turned off, the cell capacitor nodes connected to the cell transistors are left in a high impedance state for the remainder of the write phase and the entire read phase. Therefore the charge at these nodes is conserved and only three parasitic capacitances influence the dc transfer function of a memory cell []. One is the capacitance C pi, the second is the gate overlap capacitance of the read switch C ri, and the third is the capacitance C pp between the inverting input and the output of the amplifier. In the proposed memory the voltage across the sampling capacitor is read out during the readout phase. When memory cell i is selected for readout, the voltage at the output of the amplifier, oi, can be described as a function of the input voltage in [] in the form oi = A i in + offi () where A i is the gain factor and offi is the offset volt- age. The sampling capacitance C i can be made large compared to C pp and to C ri. Also, the open-loop amplifier gain is large enough in practical COS circuits. With these approximations and supposing that the reference voltage C is set to the bias voltage B the gain factor A i is given by A i = and the offset voltage offi offi =, + C pp C i (5) + C pi pwi : (6) C i Because both A i and offi are independent of the input voltage in, as indicated by ()-(6), it follows that the output voltage of the analog memory o is a linear function of in. For the Cherenkov application, where a high input bandwidth is required, the write transistor must be made large because the cell bandwidth B is determined by the size of the sampling capacitor and the resistance of the write transistor: B = n C ox W wi L wi ( H, C, T ) C i : () Since the cell capacitor nodes connected to the cell transistors remain floating after the write switch is turned off, care must be taken to ensure that no leakage occurs at those nodes, for all possible ac and dc input signals, during the write and read phases []. To avoid subthreshold leakage, the maximum input voltage swing in in the write phase is limited to in C, L (8) For the same reason, the maximum voltage swing oi at the output of the amplifier must be less than B, L during the read phase. The corresponding

4 3 5 bias ref 6 3 ref Fig.. Schematic of the folded cascode amplifier. out limit for the input voltage swing during the write phase is then in = oi A i B, L A i (9) Each channel of the analog memory architecture includes on-chip an operational amplifier used during the readout phase []. The folded cascode amplifier shown in Fig. is capable of achieving a high stable closed loop bandwidth with a large capacitive load. The circuit comprises a cascade of a common source and a common gate stage and has a p channel differential input pair. The currents through 3 and equal the sum of the currents from the differential pair, and, and from the cascode mirror formed by, 0. The reference voltages ref, ref, bias are generated by the bias generator formed by the transistors, 6. The performance results after simulations were obtained with the amplifier in follower and inverting configurations and are summarised in Table. 3 Control Circuit Description The high speed write control circuit consists of four 3 cell delay chains []. An inverter delay chain of 3 cells together with a servo feedback illustrated in Fig. 5 were implemented to reach 500 Hz sampling frequency. Each delay element in the chain consists of five OS transistors, as indicated by the shaded box in Fig. 5. A write pulse applied at input In propagates through the delay elements, producing the write address signals w < > through w < 3 > for the analog memory core. The minimum width of the write pulse In is constrained by the accuracy with which the analog signal is to be acquired and the input time constant of the sampling cell. The delay of the write pulse through the chain is set by the control In w<3> (a) (b) Aref Write Cell 3 In w<3> Aref Phi ctr In w<3> Aref Phi ctr 5 NA NO w<> w<> w<3> Phi NO NO Fig. 5. Inverter delay chain of 3 cells. t in t in +5 Rgnd t ref 6 on off Rvdda t ref 6 off on +5 ctr Fig. 6. Timing diagram of the inverter chain showing the falling edge of the last write signal w < 3 > which can be (a) before or (b) after the raising edge of the reference pulse Aref. voltage ctr which determines the on resistance of the POS transistor. The resistance together with the gate capacitance of the following inverter stage, and 5, provide an adjustable RC time delay that governs the sampling frequency of the memory. In order to ensure a delay, and thus the sampling frequency, a servo feedback circuit, also shown in Fig. 5, is used. The raising edge of a reference input signal Aref is compared to the falling edge of the last write signal w < 3 >. When the delay is less than the intended value, as shown in Fig. 6(a), the transistor 6 turns on, which connects the current generated by 8, 9 mirror current to the capacitor C. The voltage across C is increased, thereby slowing the inverter C

5 E S S0 Q3 Q Q Q0 E Q r<8> S S S0 decoder_:8 E S S0 Q3 Q Q Q0 Q0 E Q Phien E S S0 Q3 Q Q Q0 E S S0 Q3 Q Q Q0 S S S0 decoder_:8 Q0 E S S0 Q3 Q Q Q0 E Q S S S0 decoder_:8 r<> r<0> r<3> r<8> r<> Fig.. Read control circuitry. Q0 Address6 Address5 Address Address3 Address Address Address0 (a) (b) AnalogOutputCh () Reconstructed AnalogOutputCh () Time (s) Time (ns) Fig. 9. Response after simulations of one channel to a pp, Hz sine wave sampled at 500 Hz. The pulse is plotted on the (a) read and the (b) write time scale. Address6...Address0 0 Phien r<> r<> the analog input waveform. This decision is given by the microcontroller which provides the start and stop addresses through the address signals. r<8> Fig. 8. Timing diagram for the read control circuitry. chain via the control voltage ctr. The signal Phi is included in such a way that the voltage across C is modified only while the delays are being compared during the write phase. In the same way, as illustrated in Fig. 6(b), when the delay is larger than the intended value, the voltage across C is decreased. The time difference t ref,t in determines the resulting write sample frequency, f s =3=(t ref,t in ). The wires Rgnd and Rvdda are connected outside of the chip to external resistors. The size of the resistors determines the speed of charge or discharge of the capacitor C during the write phase. The readout of a memory channel is controlled by on-chip of 8 decoder shown in Fig.. The schematic consists of of decoders and of 8 decoders implemented with standard digital gates. A microcontroller which exists in the camera electronics design of the Cherenkov telescope [] provides bit address signals Address0 through Address6, as illustrated in Fig. 8. The signal P hien activates the decoders and thus enables the read signals r < > through r<8 >. For the Cherenkov application is necessary to read out only a few samples depending of Circuit Implementation The response after simulations of one channel to a peak-to-peak input sine waveform is shown in Fig. 9(a) and illustrates the operation of the circuit with C and B set to.5. The output signal alternates between the output levels of the 8 cells and the bias level, B, as illustrated in Fig. 3. The readout time for each cell was set at s andthe reset time at s. In Fig. 9(b) the output pulse is plotted as a function of input time. The acquisition time of the analog memory for a given accuracy is less than 0.5 ns. The layout of the FASTSAP- chip shown in Fig. 0 was designed at ASIC laboratory in the Austria icrosystems (AS) 0.8 m COS technology and then submitted to the Nordic LSI ASA company in Norway. The prototypes are expected to come and the experimental setup is ready for measurements. The circuit has been carefully laid out to minimise the parasitic capacitances and the coupling between the control and signal traces. The banks of analog memory cells are placed in the middle of the layout. The inverter chains are located above the analog memory channels and the read control circuit is below those channels. The large input transistors of the input switches are seen on the left and the amplifiers appear on the right of the analog memory channels.

6 Fig. 0. Layout view (3.6 mm x 3.39 mm) of the experimental chip FASTSAP-. 5 Conclusion In analog waveform applications switched capacitor memories can provide superior performance with respect to cost, space, sampling rate, and power dissipation when are compared to flash A/D converters. This paper describes a memory architecture that enables sampling rate of 500 Hz by using inverter delay elements with on-chip delay feedback compensation. The inverter chain avoids the need for a high speed external clock and is insensitive to variations in the fabrication process as well as to variations in the temperature and supply levels. The high speed write signals are confined to a small area on the chip and therefore the perturbations from the external clocks are avoided. In the proposed circuit, memory cell pedestals are independent of the input signal amplitude and can be eliminated by analog or digital subtraction. The proposed analog memory is an alternative for the camera electronics of the Cherenkov telescope where continuous data acquisition is not required. References: [] G. Haller, High-speed, High Resolution Analog Waveform Sampling in LSI Technology, Ph.D. Thesis, Stanford U.S.A., arch 99. [] Cristian Chiţu and Werner Hofmann, High Speed Analog emory Integrated Circuit for Cherenkov Telescopes, Proceedings of the first IEEE Asia Pacific Conference on ASICs, Seoul, Korea, August 3-5, 999, pp [3] W. Hofmann et al., An Array of Imaging Atmospheric Cherenkov Telescopes for Stereoscopic Observation of Air Showers from Cosmic Gamma Rays in the 00 Ge Energy Range, ax-planck- Institut für Kernphysik Heidelberg, arch, 99. [] W. Hofmann et al., Design of Camera Electronics for HESS, ax-planck-institut für Kernphysik Heidelberg, November, 998. [5] B. Sheu and C. Hu, Switch-Induced Error oltage on a Switched Capacitor, IEEE J. Solid State Circuits, vol. SC-9, August 98, pp [6] J. Shieh,. Patil, and B. Sheu, easurement and Analysis of Charge Injection in OS Analog Switches, IEEE J. Solid State Circuits, vol. SC-, April 98, pp. -8. [] P. Gray and R. eyer, OS Operational Amplifier Design - A Tutorial Overview, IEEE J. Solid State Circuits, vol., December 98, pp

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