ANITA ROSS Trigger/Digitizer/DAQ. Gary S. Varner University of Hawai, i, Manoa ANITA Collaboration JPL March 2004

Transcription

1 ANITA ROSS Trigger/Digitizer/DAQ Gary S. Varner University of Hawai, i, Manoa ANITA Collaboration JPL March 2004

2 Overview System overview Reiterate, with ROSS simplifications ROSS trigger descope System descope Buffer depth Sampling record Critical R&D Items Largely the same STRAW3 LABRADOR as is More detail on LABRADOR 1

3 Proposed Signal Flow Trigger LNA Gain [GHz] Digitize [GHz] 2

4 Updated August 03 Baseline ANITA Sampling Unit for RF (SURF) Board 3

5 ROSS Single-Crate Scheme During Aug 2003 Collab Meeting challenged to go to 4 Antenna/Digitizer Card Transition module TURF boards CPU Crate Top View PCI bus 1 PCI bus 2 7 drops max 40 channel scenario 4 antenna SURF boards 4 spare cpci slots for other functionality (GPS, housekeeping?) 4

6 STRAW3 Data Sheet Available on the ID Lab web-site A number of SPICE Simulations of Performance Expectations 5

7 STRAW Architecture 0.25µm TSMC process 6

8 Self-Triggering 7

9 Digital-to-Analog Convert Fine-adjust DAC Main DAC DAC Code 8

10 Fine Adjust R 2R 9

11 Triggering Detail 10

12 Discriminator Layout Fast Comparator Control Logic Capacitor 11

13 Simulation Results Use simulated high freq. Response from beamtest data: works 12

14 RFCeval 0 th order prototype Quick Reference: RFCeval == Radio Freq Comp evaluation board STRAW == Self-Triggered Recorder for Analog Waveforms LABRADOR == Large Analog Bandwidth Recorder And Digitizer with Ordered Readout 13

15 TURFpro project Prototyping: On-board amps Limited Multi-banding RF power monitoring Local trigger processor Sr. EE Project Develop Feedback Control Loop By defn will be Done by end of Semester DACs DACs 32-b scaler 32-b scaler Other Projects Considering 2-chip soln: Super-RICE SKAM 14

16 Updated August 03 Baseline ANITA Sampling Unit for RF (SURF) Board 15

17 LABRADOR Goals Maximum input bandwidth 50Ω impedance Simplified architecture (no trigger functionality) best RF coupling into Switched Capacitor storage cells Classical engineering trade-offs Input trace resistance vs. load capacitance Storage capacitor ktc noise vs. load capacitance Storage switch R on vs. drain load capacitance Analog Transfer Optimum speed Individual channel parallel Improved ADC Ramp type no missing codes Massively parallel to reduce conversion time Today s part See SMEX Talk 16

18 LABRADOR Architecture 0.25µm TSMC process 17

19 LABRADOR floorplan Straight Shot RF inputs 128x Wilk ADCs Analog Superbuffers 8 chan. * 256 samples 8x HS Analog out, 1x MUX out Random access: 18

20 STRAW ADC Expectations worst case for mismatch in a previous implementation of same SAR ADC w/r-2r ladder Can correct to rather linear, but still differential sensitivity and calibration is a pain Wilkinson type better monotonic BUT, slower 19

21 Wilkinson ADC No missing codes Linearity as good as can make ramp Can bracket range of interest + - NB: SCA output not linear 20

22 ADC Sim Wilkinson ADC SPICE Sim Output code [counts] y = x R 2 = Wilk ADC Linear (Wilk ADC) Input Voltage [V] 21

23 Transfer Curve Storage Cell Simulation v kt C rms = = 0. 5 store mv Diff sensed Voltage (Vout) [mv] Gain: Rload = 40k y = x R 2 = Stored Waveform (Vin) [mv] 22

24 Readout speed comparison IC STRAW2 - GEISER STRAW2 DALI ADC EXT EXT speed 8MHz 1MHz Total Latency 384 µs 3,072 µs Evt. Size 6kB STRAW3 -- SURF STRAW3 -- FINESSE INT EXT 2.5MHz 10MHz (a) 1,638 µs 410 µs 8kB LABRADOR -- SURF INT 100kHz (b) 240 µs LABRADOR -- serial EXT 10MHz 210 µs 4kB LABRADOR -- parallel EXT 20MHz 12.8 µs (a) 16 channels for STRAW3, 12 channels for STRAW2 (b) 12.8MHz effective: 128x ADC; 100MHz clock, 12b eff. includes additional latency 8x 20MHz ADC in parallel (>300MB/s!!) 23

25 Aside: LABRADOR sampling speed High/Low CTRL: Extend to 4 GSa/s Improve odd/event Low freq operation Sampling Freq. [GHz] STRAW2 Sampling Freq. Avg. -cycle +cycle SPICE Freq. Adj. Voltage (ROVDD) [V] 24

26 ROSS Delineations Greatly simplified Global Trigger Most logic done locally > 1 bit/surf? L1 trigger only VETO? 2x Buffer depth Compromises on the trigger banding? Reduced RF monitoring No active RF pulser circuit Depend upon Noise Diode Any problem with this? 25

27 Summary R&D into critical (non-standard) components: Good progress on meeting specs Pending write-ups (works in progress): LABRADOR Data Sheet ( RFCeval Testing Summary Plans: RFCeval board in debug STRAW3 chip alive LABRADOR returns ~ now (also test on RFCeval) Plan to leverage interest of other groups on testing Design conflict: SMEX vs. ROSS 26

28 Back-up slides 27

29 Askaryan Signature Time (ns) Significant signal power at large frequencies Strong linear polarization (near 100%) 28