Tomoyuki Saito (Tohoku Univ.) Outline

Size: px

Start display at page:

Download "Tomoyuki Saito (Tohoku Univ.) Outline"

Prudence Powell
5 years ago
Views:

1 1 Development of Readout system for FPCCD Vertex Detector Tomoyuki Saito (Tohoku Univ.) H. Ikeda A, K. Itagaki, A. Miyamoto B, Y. Takubo, Y. Sugimoto B, H. Yamamoto Outline FPCCD Vertex Detector Readout ASIC FPCCD readout test Summary 2010/10/ IWLC CERN, CICG A JAXA B - KEK

2 FPCCD Vertex Detector FPCCD (Fine Pixel CCD) Pixel size : 5µm 5µm Sensitive thickness : 15 µm Total channel : 6080ch pix/ch Total pixel : ~10 10 pixel Full depleted Very large Tomoyuki Saito ( Tohoku U.) 2 Prototype-FPCCD to establish technology Pixel size : 12µm 12µm Sensitive thickness : 15 µm Readout channel : 4ch pix/ch Prototype-FPCCD 2

3 3 Requirements for FPCCD Requirements for FPCCD Readout speed > 10Mpix/s All pixels is read out in the inter-train time. Noise level < 50 electrons Signal level is ~500e. Power Consumption < 100 W (16mW/ch) VTX is put in cryostat. Beam structure ~2ms ~200ms ~2ms 1train 1pixel 5µm 15µm ~500e ~1500e Readout ASIC was designed to satisfy these requirements.

4 Test of Readout ASIC Tomoyuki Saito ( Tohoku U.) 4

5 5 Readout ASIC Requirements for ASIC Readout speed > 10 Mpix/sec Noise level < 30 electrons Power consumption < 6mW/ch Prototype-ASIC Measures Design of readout ASIC Charge sharing ADC 10 µw/ch ADC 5 Mpix/sec 2 Output CCD output Pre-amplifier LPF CDS Noise suppression ADC LVDS driver

6 6 Performance of readout ASIC Noise level of readout ASIC was measured. Pedestal distribution at 1.5Mpix/s RMS= ADC=40e ADC Noise level (Room temperature) RMS = 0.52 ADC count ~21 electrons (Goal : 30 e) The noise level satisfies the requirement.

7 7 Performance of readout ASIC Noise level of readout ASIC was measured. Pedestal distribution at 1.5Mpix/s 1 Problem Design value : 10Mpix/s 2 Pedestal distribution RMS= ADC=40e No -3 output ADC Noise level (Room temperature) RMS = 0.52 ADC count ~21 electrons (Goal : 30 e) Some ADC counts are missing. The noise level satisfies the requirement.

8 8 For next prototype-asic 1 The problems on the current ASIC will be solved in the next ASIC. Problem 1 Readout speed : Max 1.5Mpix/s (Goal :10Mpix/s) 2 Some ADC counts don t output. Solution to Problem11 The current in the comparator is too small for high speed readout. The power lines for ADC are increased Number of pad :

9 9 For next prototype-asic 2 Problem 1 Readout speed < 1.5Mpix/s (Goal :10Mpix/s) 2 Some ADC counts don t output. 60 Solution to Problem2 ADC cou unt Capacitor = bit Input voltage (mv) The capacitance in ADC is shifted from design value by the stray capacitance in the switching circuits Number of transistors used in the switch Capacitance We will submit new ASIC modified on these problems on next February.

10 10 For next prototype-asic 2 Problem 1 Readout speed < 1.5Mpix/s (Goal :10Mpix/s) 2 Some ADC counts don t output. 120 Solution to Problem2 ADC cou unt Capacitor = bit Input voltage (mv) The capacitance in ADC is shifted from design value by the stray capacitance in the switching circuits Number of transistors used in the switch Capacitance We will submit new ASIC modified on these problems on next February.

11 Readout of FPCCD Tomoyuki Saito ( Tohoku U.) 11

12 12 Test bench FPCCD Data Readout ASIC Operation signal Readout board Operation signal Data FPGA SiTCP FPGA Control Data (Ethernet) Readout test of FPCCD is performed by this test bench.

13 CCD readout test : Pedestal The pedestal of CCD is checked. CCD image of pedestal (ADC count) Sensor region Pedestal distribution for1line (60th line) ADC The difference between pixels is small. Pixel position

14 14 CCD readout test : Test with LED CCD is covered with the photo mask and radiated by LED light. Photo mask (made of brass) Character size : 1mm 1mm Line width : 0.2 mm Photo mask 1 mm 1 mm CCD image with photomask Success in reading ILC image!

15 15 Plan Summary and Plan We have developed the readout system for FPCCD. Result of performance test Readout ASIC Readout speed : 1.5Mpix/sec (Goal : 10 Mpix/sec ) Noise level : 21eletrons (Goal : 30e) CCD sensor + Readout system Able to read picture Readout ASIC Next prototype for ASIC will be made on next February Readout speed : Our goal (10Mpix/sec) will be reached. FPCCD readout test Radiation test

16 Back up

17 17 Correlated double sampling circuit (CDS) The difference on voltages between the reset and the signal level is measured. Sampling CCD signal Charge information Able to remove the noise from the amp and reset. Reset Sampling We can measure the only charge information of pixels.

Development of Readout ASIC for FPCCD Vertex Detector

1 Development of Readout ASIC for FPCCD Vertex Detector Tomoyuki Saito (Tohoku University) Y. Sugimoto, A. Miyamoto, Y. Takubo (KEK) H. Ikeda (JAXA), H. Sato (Shinsyu) K. Itagaki, H. Yamamoto (Tohoku)