Development of SiTCP Based Readout System for Pixel Detector Upgrade in ATLAS Experiment
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1 Development of SiTCP Based Readout System for Pixel Detector Upgrade in ATLAS Experiment J.J. Teoh, K. Hanagaki, M. Garcia-Sciveres B, Y. Ikegami A, O. Jinnouchi D, R. Takashima C, Y. Takubo A, S. Terada A, Y. Unno A, ATLAS Silicon Japan Group. Osaka University, KEK A, LBNL B, Kyoto University of Education C, Tokyo Institute of Technology D March 2013 JPS 68 th Annual Meeting 1
2 Intro: ATLAS Detector Pixel Detector - A Toroidal LHC Apparatus - goals: search for Higgs boson, SUSY, and extra dimensions... 2
3 Intro: Pixel Detector 430mm 1442mm Inefficiency (%) FE-I3 s inefficiency HL-LHC L=5x10 34 cm -2 s -1 L=3x10 34 cm -2 s -1 LHC L=10 34 cm -2 s -1 End-cap layers purpose: - vertexing - tracking ~80M channels. Barrel layers current readout IC: FE-I3 hit rate/dc inefficiency due to: - pile-up - non-local buffer - FE-I3 s data transfer mechanism --- transfer every hit. complete replacement in High Luminosity-LHC (HL-LHC) upgrade (~2022); L =5x10 34 cm -2 s -1 3
4 10.8mm 19mm Intro: New Front End IC FE-I4 20mm Pixel size (µm 2 ) FE-I3 FE-I4 50 X x 250 Pixel array (total #) 18 X 18 (2880) 80 x 360 (26880) FE-I3 Data Rate (Mb/s) mm FE-I4 replacing FE-I3 - to cope with higher hit rate. - radiation hard. - increase tracking resolution. Main improvements in FE-I4 - smaller pixel size - local buffer - transfer only hit that are triggered. r 4
5 Intro: Existing R/O System Roles: USBpix System i) electronic test bench ii) DAQ system for sensor + FEI4 module RCE System ATCA Crate Compact Size USBpix Yes RCE No Convenience No No Fast r/o speed Versatility (software) 4-chip r/o No No No Yes No Yes 5
6 Motivation Why a new readout (r/o) system? i) i) compact and convenience. ii) i) high speed & versatility. USBpix SEABAS RCE iii) ii) MUST have 4-chip r/o scheme. 4-chip assembly prototype Compact Size Yes No Convenience No No Fast r/o speed Versatility (software) 4-chip r/o No No No Yes Yes Yes Yes Yes Yes No Yes 6
7 Power in FE-I4 10cm ser FPGA SiTCP FPGA by T. Uchida (KEK) 18.5cm 4-chip daughter board SEABAS R/O System Overview *SEABAS - developed by SOI collaboration compact physical size NO need for large dedicated hardware convenient with implementation of SiTCP hardware based TCP/IP processor. networking capability. Power in DAQ software Ethernet hardware ready for 4- chip r/o. 7
8 FE-I4 Power in 4-chip daughter board My tasks Firmware & Software Credit to Y.Takubo (KEK) User FPGA SiTCP FPGA Power in SEABAS Ethernet Firmware functionalities: - forwarding command bit pattern. - data flow control. - decoding. Software functionalities: DAQ software - routines (configuration etc.). - data extraction and analysis. 8
9 DAQ Flow (using FE-I4 internal calibration circuit) Configure global and local pixel reg. Calibration pulse or Charge Send Trigger Read out Decode Pixel Analog Circuit Tuning Tuning Global Reg. Trigger Readout Charge Pixel s Reg. Digi. pulse Decode 9
10 Eff. Pixel Analog Circuit Tuning Tuning Global Reg. Trigger Readout Charge Pixel s Reg. Decode Eff Threshold 2! / ndf / 1 Prob Mean_Vth 4001 ± 23.6 Noise ± 26.8 Noise ~114e - Injected Charge Scan - charges can be injected correctly. - discri. threshold can be measured # injected e Injected Charge (e - ) - FE-I4 specification: noise < 300e -. 10
11 #entries #entries Threshold Distribution_(before threshold tuning) Before Entries Mean 2528 RMS Threshold (e-) Threshold Distribution_(after threshold tuning) After thavg: 2528e - σ : 455e - Threshold (e - ) h1 Entries Mean 2998 RMS thtarget: thavg: e - σ : 78e - Charge Pixel Analog Circuit Tuning Tuning Pixel s Reg. Global Reg. Threshold Tuning - even at same setting, each pixel may have different threshold. - adjust local reg. to change discriminator threshold. Trigger Readout Decode - each pixel can be accessed and tuned Threshold (e - ) Threshold (e-) - tuned threshold dispersion < 100e - 11
12 Readout Speed Take threshold tuning (longest time) as a benchmark: USBpix: 40~50 min RCE: ~23 min target: faster or at least ~23 min through efficient software alg. & firmware design. firmware decoder efficient way to retrieve data from kernel buffer optimization of trigger interval, ttrig Retrieval Method Decoder Ttrig (ms) Tother (s) Tdata retrieval (s) Tdecode (s) Ttotal (s) nbytes/ operation Firmware Final result: ~22 minutes 12
13 Ongoing works Credit to Y.Ikegami 氏 (KEK) 4-chips daugther card 4-chips Board expansion to 4-chips parallel readout (in progress) 13
14 Conclusion New readout system for FE-I4: - as a electronic test bench. - as DAQ sys. for sensors + FE-I4 incorporated the qualities of existing system - compact, convenient. Achieved high readout speed. Expansion to 4-chip parallel readout is in progress. 14
15 Additional Slides 15
16 16
17 Pixel Analog Circuit Tuning Tuning Global Reg. Trigger Readout Pixel s Reg. Digi. pulse 13 Decode row Row Occupancy: Digital Injection 100 Time Over Threshold Digital Injection Test every 3 rd row, masked col V_th - configuration is successful TOT 13 - decoder is working col 0 Column TOT 17
18 Analog Circuit ing Tuning Global Reg. Trigger Readout entries hits L1 Latency Scan ixel s Reg. Digi. pulse Decode Trigger test L1 Delay latency - trigger is sent at the correct timing. 40MHz Clk Discri. output Latency counter LV1 trigger latency correct timing; read out 18
19 DC EODC EODC 19
20 pixel memory T: read token R: Read flag N: neighbor logic inputs D: Discriminator input 20
21 Ttotal Tconfiguration Tother Tdaq Tdata_retrieval Tdecoding Twaiting Tcopying T8b/10b Tdecode_alg 21
22 function: select() Check input port readiness twaiting function: select() Check input port readiness twaiting function: ioctl() function: ioctl() function: recv() Timeout? NO Check how much data is available YES tcopying Check how much data is available function: recv() Write nbytes data into user buffer tcopying Write nbytes data into user buffer Decoding tdecode Decoding NO Trig_sent == # trig? tdecode NO Trig_sent == # trig? YES YES (b) (a) 22
23 FE-I4 SEABAS SiTCP Controller Slow & Fast Cmds Firmware Ctrl Cmd Data Acquisition CMD Generator Configuration Injection INJ Calibration OPR Tuning DAQ CNFG DAQ & Control Software Analysis Tool DOUT 23
24 FE-I4 FIFOs LV1 Trigger, CAL Pulse Configuration Relay 8b/10b decoder Signal_Reader Channels_Manager Signal_Sender Reset Job_Manager User FPGA DCM & Clk_Gen Cmd_Decoder SiTCP Communicator Trig_Manager Top_module SEABAS SiTCP FPGA PC 24
25 Software SEABAS FE-I4 START Establishing TCP connection Send FE-I4 global register configuration commands Power-up Reset Send registers reset commands Power-up Reset Send pixel local register configuration command Send DAQ start signal Sending calibration & LV1 cmd output 8b/10b encoded data decode 8b/10b encoded data send decoded data Receive data NO NO Trig_sent == # trig? YES All pixels done? NO Trig_sent == # trig? YES IDLE IDLE YES END 25
26 Hit Map (Digital Test triggers) Time Over Threshold (TOT) (a) (b) 26
27 i) Digital & Analog Injection Test, ii) VCal Scan, iii) GlobalDAC Tuning, iv) Global Preamp Ifeedback Tuning v) Threshold Tuning, vi) TOT Tuning, vii) Noise Occ. Scan, viii) Double_Triggers Scan, etc
28 #entries! TOT distribution with only Small Cap. On 3 Entries Mean RMS #entries TOT distribution with only Big Cap. On 3! Entries Mean 6.5 RMS TOT(unite: BC) TOT(unite: BC) Pixel Analog Circuit Tuning Tuning Global Reg. Trigger Readout 2 injection capacitors Charge Pixel s Reg. Decode 28
29 2200 Entries Noise Distribution Mean RMS ENC (e-) 29
30 #entries Threshold Distribution_(before Threshold_Tune) h1 Entries Mean 2078 RMS Row Threshold Map_(before TDAC_tune) 300 Before Threshold (e-) Threshold Distribution_(after Threshold_Tune) #entries h1 Entries Mean 2000 RMS Threshold (e-) Threshold Scatter Plot_(after TDAC_tune) Threshold (e-) Row σth: 419e - 60e - Threshold Tuning Threshold Map_(after TDAC_tune) After -Threshold tuned to 2000e Col TOT Tuning TOT tuned to e - 30
31 Pixel Analog Circuit TOTavg: 9.9 σ : 1.5 TOTavg: 6.3 σ : 0.7 Ifb Tuning Tuning Global Reg. TOTtarget: 20000e - Charges Pixel s Reg. TOT (BC) TOT (BC) Before After Time Over Threshold Tuning - each pixel can be accessed and tuned. - charge info. can be extracted. - decoder is working correctly. 31
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