SVT-Pixel layer 0 recent achievements on chip readout architectures

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1 SVT-Pixel layer 0 recent achievements on chip readout architectures Filippo Maria Giorgi - INFN and University of Bologna on behalf of the VIPIX collaboration XII SuperB General Meeting Annecy, March 5 th - 9 th 200

2 Boundary target conditions Matrix architecture comparisons Pixel architecture Matrix scan logic Sparsification and readout scheme Integration achievements Simulations results Improvements Conclusions Summary

3 Rate on Area: 00 MHz/cm 2. Matrix area ~.2-.3 cm 2. Pixel pitch ~ 50 μm Matrix dimension 256x92 pixels Architecture tailored for hybrid /3DMAPS sensor Output bus bandwidth ~ 20bit@200MHz (4Gbps) Target Conditions

4 Previous matrix architectures (2D MAPS): - Simple in pixel digital logic (competitive N-Well) - Time labeling of hits relayed to external logic - No hit information from every single pixel (scalability limits) group of 6 pixels: Macro Pixel (MP) with single Fast-OR freezing logic (avoid hits belonging to different Time Windows (BC clock) to populate the same MP) increase of dead area proportional to MP area trade off scalability vs efficiency - Moreover: time ordered hit extraction from the matrix requires great amounts of memory to store maps of MPs to be scanned for a determined TS (Scan Buffer). New matrix architecture (Hybrid or 3D MAPS): - Dense in pixel digital logic (Time labeling, arbitrary TS comparator for time ordered readout, auto pixel latch reset ) - Still no hit information from every single pixel (same 2D scalability limits) Column fast-or BUT NOW TS at pixel level NO FREEZING required much less dead area NO memory required (Scan Buffer) to perform time ordered matrix scans Smaller BC periods allowed (no scan buffer overflows, single col. Sweep..) Matrix architectures comparison

5 Analog front-end Threshold comparator Hit latch Time counter TS latch Comparator Reading Time Stamp See internal presentations by F. Morsani et al. Column Fast-Or New pixel FAST-OR architecture

6 Analog front-end Threshold comparator Hit latch PXL_DATA_BUS Reading Time Stamp TS latch Comparator See internal presentations by F. Morsani et al. COL_ENABLE New pixel READOUT architecture

7 Time counter During time window some pixel get fired Matrix scan Logic

8 Time counter During time window some pixel get fired Matrix scan Logic

9 Time counter During time window some pixel get fired Matrix scan Logic

10 2 Time counter During time window 2 some other pixel get fired Matrix scan Logic

11 2 Time counter 2 2 Reading Time Stamp 2 During time window 2 some other pixel get fired And reading of TS= hits start Matrix scan Logic

12 Time Stamp comparator MATCH 2 Time counter 2 2 Reading Time Stamp 2 Matrix scan Logic Column Fast-OR During time window 2 some other pixel get fired And reading of TS= hits start

13 PIXEL_DATA_BUS Reading Time Stamp COL_ENABLE Colum sweep: - Only the columns hit are scanned - clock cycle per column, indep. of occupancy Matrix scan Logic

14 PIXEL_DATA_BUS Reading Time Stamp 2 0 COL_ENABLE Colum sweep: - Only the columns hit are scanned - clock cycle per column, indep. of occupancy Matrix scan Logic

15 PIXEL_DATA_BUS Reading Time Stamp Matrix scan Logic COL_ENABLE Colum sweep: - Only the columns hit are scanned - clock cycle per column, indep. of occupancy

Pixel organized into 4 sub-matrices Each sub-matrix has an independent scan logic Increase horizontal parallelization The shorter the scans the greater the

preserved) Readout Submatrix0 (64x92) Submatrix (64x92) Submatrix2 (64x92) Submatrix3 (64x92) Readout Readout Readout SWEEPER SWEEPER SWEEPER SWEEPER Time

16 Pixel organized into 4 sub-matrices Each sub-matrix has an independent scan logic Increase horizontal parallelization The shorter the scans the greater the effi. One readout for each sub-matrix Vertical parallel sparsification (one entire column per clock cycle) Hit encoding Hit de-queuing system (time sorting preserved) Readout Submatrix0 (64x92) Submatrix (64x92) Submatrix2 (64x92) Submatrix3 (64x92) Readout Readout Readout SWEEPER SWEEPER SWEEPER SWEEPER Time counter (Gray or BCD) Slow Control Readout Scheme Common output stage ~ 4Gbps bandwidth I 2 C-like external interface: - 2 pad per chip - 2 lines for entire module

17 All the readout architecture coded in synthsizable VHDL. Sweeper for new matrix architecture rewritten from scratch. Full architecture entirely integrated reusing the same readout components from SuperPX0 alias FE4D32x28. We want to recycle as much as possible of them: Sparsification algorithms (zone sparsification) Barrel architecture (dynamic asymmetric FIFOs: variable input width) Concentrators with time sorting preserving algorithms. Integration achievements

18 . High statistic simulations with Matrix and Sweeper ONLY: The evaluated inefficiency depends only on how long it takes to extract a hit from the matrix. No readout no readout bottlenecks taken into account. 2. High statistic simulations of the whole architecture: New matrix New sweeper OLD SuperPX0 readout AS IS (sparsification and dequeuing logic). Simulations overview

19 . High statistic simulations with Matrix and Sweeper ONLY: The evaluated inefficiency depends only on how long it takes to extract a hit from the matrix. No readout no readout bottlenecks taken into account. 2. High statistic simulations of the whole architecture: New matrix New sweeper OLD SuperPX0 readout AS IS (sparsification and dequeuing logic). Simulations overview

Linear BC span 00 50 200 250 300 350 400 450 500 000 500 2000 0 99,97 99,95 99,95 99,93 99,9 99,90 99,88 99,87 99,87 99,78 99,70 99,64 2 99,96 99,95 99,95 99,92 99,9 99,89 99,88 99,86 99,86 99,77

99,85 99,84 99,73 99,66 99,58 22 94,33 99,07 99,89 99,89 99,88 99,87 99,85 99,84 99,84 99,73 99,65 99,57 25 93,95 92,73 95,86 99,72 99,85 99,85 99,84 99,83 99,83 99,72 99,63 99,55 30 89,3 89,20 88,78

20 Linear BC span ,97 99,95 99,95 99,93 99,9 99,90 99,88 99,87 99,87 99,78 99,70 99, ,96 99,95 99,95 99,92 99,9 99,89 99,88 99,86 99,86 99,77 99,70 99, ,95 99,95 99,94 99,9 99,9 99,89 99,87 99,86 99,85 99,76 99,68 99,6 8 99,93 99,93 99,92 99,9 99,89 99,88 99,86 99,86 99,85 99,74 99,67 99, ,40 99,9 99,9 99,90 99,89 99,87 99,86 99,85 99,84 99,73 99,66 99, ,33 99,07 99,89 99,89 99,88 99,87 99,85 99,84 99,84 99,73 99,65 99, ,95 92,73 95,86 99,72 99,85 99,85 99,84 99,83 99,83 99,72 99,63 99, ,3 89,20 88,78 87,92 88,07 9,8 93,89 96,34 98,70 99,69 99,6 99,5 BC (ns) RDclk(ns) Respect to previous matrix architectures : Wider margin on MST>BC condition (no scan buffer) Higher efficiencies (no freezing) Mean Sweeping Time (MST) > BC Since we perform an independent sweep for each BC period, this is an UNAFFORDABLE WORKING CONDITION NO sensor efficiency NO pixel reset dead time ONLY SWEEPING DEAD TIME. Matrix+Sweeper simulations

21 Linear BC span ,97 99,95 99,95 99,93 99,9 99,90 99,88 99,87 99,87 99,78 99,70 99, ,96 99,95 99,95 99,92 99,9 99,89 99,88 99,86 99,86 99,77 99,70 99, ,95 99,95 99,94 99,9 99,9 99,89 99,87 99,86 99,85 99,76 99,68 99,6 8 99,93 99,93 99,92 99,9 99,89 99,88 99,86 99,86 99,85 99,74 99,67 99, ,40 99,9 99,9 99,90 99,89 99,87 99,86 99,85 99,84 99,73 99,66 99, ,33 99,07 99,89 99,89 99,88 99,87 99,85 99,84 99,84 99,73 99,65 99, ,95 92,73 95,86 99,72 99,85 99,85 99,84 99,83 99,83 99,72 99,63 99, ,3 89,20 88,78 87,92 88,07 9,8 93,89 96,34 98,70 99,69 99,6 99,5 BC (ns) RDclk(ns) Respect to previous matrix architectures : Wider margin on MST>BC condition (no scan buffer) Higher efficiencies (no freezing) Mean Sweeping Time (MST) > BC Since we perform an independent sweep for each BC period, this is an UNAFFORDABLE WORKING CONDITION NO sensor efficiency NO pixel reset dead time ONLY SWEEPING DEAD TIME. Matrix+Sweeper simulations

22 Linear BC span ,97 99,95 99,95 99,93 99,9 99,90 99,88 99,87 99,87 99,78 99,70 99, ,96 99,95 99,95 99,92 99,9 99,89 99,88 99,86 99,86 99,77 99,70 99, ,95 99,95 99,94 99,9 99,9 99,89 99,87 99,86 99,85 99,76 99,68 99,6 8 99,93 99,93 99,92 99,9 99,89 99,88 99,86 99,86 99,85 99,74 99,67 99, ,40 99,9 99,9 99,90 99,89 99,87 99,86 99,85 99,84 99,73 99,66 99, ,33 99,07 99,89 99,89 99,88 99,87 99,85 99,84 99,84 99,73 99,65 99, ,95 92,73 95,86 99,72 99,85 99,85 99,84 99,83 99,83 99,72 99,63 99, ,3 89,20 88,78 87,92 88,07 9,8 93,89 96,34 98,70 99,69 99,6 99,5 BC (ns) RDclk(ns) Respect to previous matrix architectures : Wider margin on MST>BC condition (no scan buffer) Higher efficiencies (no freezing) Mean Sweeping Time (MST) > BC Since we perform an independent sweep for each BC period, this is an UNAFFORDABLE WORKING CONDITION NO sensor efficiency NO pixel reset dead time ONLY SWEEPING DEAD TIME. Matrix+Sweeper simulations

23 SWEEPING Efficiencies (%) 99,95 99,90 99,85 99,80 99,75 99,70 99,65 99,60 RD (ns) ,55 99, BC (ns) NO MST>BC points plotted. Matrix+Sweeper simulations

24 . High statistic simulations with Matrix and Sweeper ONLY: The evaluated inefficiency depends only on how long it takes to extract a hit from the matrix. No readout no readout bottlenecks taken into account. 2. High statistic simulations of the whole architecture: New matrix New sweeper OLD SuperPX0 readout AS IS (sparsification and dequeuing logic). Simulation overview

25 Modelsim TCL script Packages Sources Matrix Test Bench VHDL VHDL VHDL VHDL Compiler Parameter lists for the loop Work library Looped VSIM Simulator Hits cross-check C++ Program invoked Sim Reports For synthesis Hit cross-check report Sim. only 2. Full architecture simulations

26 Matrix VHDL Behavioral model of digital pixel logic Tunable Monte Carlo for hit generation at pixel level Efficiency evaluation logic Test Bench VHDL Consistency check of package parameters (dimensions, subdivisions ) Chip acquisition initialization through Slow Control port (I 2 C emulation) ASCII reports for the cross check of the hits Generated hits report (Monte Carlo report) Readout hits report (Output Data Bus report) General simulation report sim. properties parameters efficiencies monitors. 2. Full architecture simulations

27 Efficiency results: - High statistic runs: - 2ms simulated per run ~250K hit per run - 5h CPU time per run - Again NOT taken into account: - sensor efficiency (assumed 00%) - pixel reset dead time (assumed few ns) BC (ns) RD (ns) Values averaged over the 4 submatrices. - Consistent with sweeper+matrix only simulations - Readout de-queuing efficiency 00% (no barrel overflows) - Hit check results: 00 % match. - Fast_clock 4 x RDclk (output bus frequency) 2. Full architecture simulations

28 Efficiency results: Compare with SuperPX0. Improvements mainly due to: - Reduced pixel dead time (no x6 factor due to MP freezed area) - No more Scan Buffer overflows BC (ns) RD (ns) efficiency results from similar simulations of SuperPX0 readout 2. Full architecture simulations

29 Simulations shows that for even smaller BC period (50 00 ns): Time sorting de-queuing algorithm suddenly slow down. (more time windows to manage more complexity) Barrel overflow more frequent. Steps already taken to reach the BC=00 ns working point: REINFORCEMENT for critical components (barrels, concentrators ) IMPROVEMENTS and OPTIMIZATION in other areas Good chances to reach 00 ns BC with few modifications. Improvements...

30 New matrix architecture modeled New sweeper logic implemented Full chip integration successful Simulations showed excellent results down to 200 ns of BC recycling SuperPX0 de-queuing system AS IS (it was designed for BC down to us). Further improvements under investigation to reach even smaller time windows and wider margins on Barrel overflows. Conclusions

Efficiency and readout architectures for a large matrix of pixels

Efficiency and readout architectures for a large matrix of pixels A. Gabrielli INFN and University of Bologna INFN and University of Bologna E-mail: giorgi@bo.infn.it M. Villa INFN and University of Bologna