SEU Hardening Techniques for Retargetable, Scalable, Sub-Micron Digital Circuits and Libraries*

Transcription

1 SEU Hardening Techniques for Retargetable, Scalable, Sub-Micron Digital Circuits and Libraries* M. P. Baze, J. C. Killens, R. A. Paup, W. P. Snapp Boeing Space and Communications Seattle, WA * Work supported by DTRA contract DTRA01-00-C-0046

2 Multi-Fab IC Design Environment Multi-Fab environments may be Manufacturing design house possessing several processes usually with some process similarity Fabless design house with access to several processes via -Single manufacturer with several processes -Third party interface, i.e. MOSIS -Independent agreements with several manufacturers 5/1/2002 2

3 Multi-Fab Issues Advantage of Multi-Fab Environment Utilization of different fabrication processes as design options Accomplished by Retargeting designs to different process technologies. or Scaling designs to smaller rules in same technology. Retargetability Ease of design transfer to different process. Bulk, EPI, N-Well, P- Well, Twin Tub, SIMOX, SOS, SOI-MESA, Twin Tub, Single Poly, Dual Poly, # Metal Layers, Resistor Types, Capacitor Types, Device Models, etc. Scalability Ease with which a design can be scaled down in feature size, without sacrificing the advantages of scaling. 5/1/2002 3

4 Retargeting and Scaling Designs Standard Digital Cell Functions VHDL Design A (8051) VHDL Design B (1773) VHDL Design C (BC30) Process A Library A Process B Library B Process B/2 Library B/2 Targeting / Scaling Synthesis 5/1/2002 4

5 Retargeting and Scaling Designs SEU Hardening cap.s, filters, redundant, Idrive, etc. HARD 2 HARD 3 HARD 1 VHDL (H2, H3) Design B (1773) VHDL(H1, H3) Design C (BC30) A-3 A-1 Process A A-2 B-1 Process B VHDL (H1, 2, 3) Design A (8051) B-2 B/2-3 Process B/2 5/1/2002 B/2-2 Targeting / Scaling Synthesis 5

6 Basic SEU Hardening Options Three Categories of SEU Hardening Techniques 1. Charge Dissipation - Consumes power 2. Temporal Filtering - Reduces speed 3. Spatial Redundancy - Consumes area Charge Dissipation & Temporal Filtering - Increase LET T Spatial Redundancy Reduce effective X-section 5/1/2002 6

7 Charge Dissipation Increase Transistor Current Drive STANDARD NAND2 VDD Sink Q COL to prevent valid pulse widths IN0 OU T where valid > register T SH IN1 VSS transistor I DRIVE > Q COL / Register T SH HARDENED NAND2 VDD Retargetability Increases area of standard cell library Scalability Speed no significant penalty Area in proportion to drive Power in proportion to drive IN0 IN1 VSS OUT 5/1/2002 7

8 Charge Dissipation Adding Capacitors in Combinational Logic 1) Keep direct hit from crossing ½ VDD - Required Cap > 2 x (Q COL / VDD) 2) Keep input transient from crossing ½ VDD Required Cap > 2 x I DRIVE x PW / VDD : however since PW ~ Q COL / I DRIVE upstream, then IN0 IN1 - Required Cap > 2 x (Q COL / VDD), independent of global I DRIVE sizing VDD + + OUT Capacitor Set Hardness Cap> 2 x (Q COL / VDD) Trade power vs speed with global transistor sizing Retargetability Implemented by adding/sizing cap s to standard soft library Scalability Speed, power, area penalties may negate many advantages of scaling 5/1/2002 8

9 Charge Dissipation / Temporal Filtering Adding Capacitors in sequential logic + + 1) Keep direct hit from crossing ½ VDD - Required Cap > 2 x (Q COL / VDD) 2) Lengthen T SH - short input transients invalid Register T SH > Q COL / transistor I DRIVE Capacitor Retargetability Implemented by adding/sizing cap s to standard soft library Scalability Speed, power penalties may negate many advantages of scaling 5/1/2002 9

10 Temporal Filtering Delay-and-Vote in Combinational logic Network delay Voting Circuit out delay delay Total Delay = 2 x Error Pulse Width ~ 2 x (Q COL / I DRIVE ) if I DRIVE = 0.25 ma and Q COL = 0.4 pc then 2 x (Q COL / I DRIVE ) = 3.2 ns Retargetability Architecture implementation. Delay element redesign for each process. Scalability If Q COL does not scale down with I DRIVE, the required delay increases 5/1/

11 Spatial Redundancy - TMR Triple Mode Redundancy (TMR) Error on OUT requires simultaneous errors in 2 or more logic networks Logic Network Does not increase LET threshold INPUTS Logic Network Voting Circuit OUT Does reduce effective cross-section by geometric probability of multiple node hit Logic Network X-sec EFF ~ 1 / (node separation) 2 ~3X power and area penalty Retargetability Architecture implementation. Modified structural netlists and/or cells Scalability Adequate separation is critical 5/1/

12 TMR - Node Separation Triple Redundant Flip/flops Vdd Bad Layout Practice 1 D CLR Q PRE - Rail stacking of voted F/F s Vdd 2 voter Q Adjacent redundant elements 3 D CLR Q PRE 5/1/

13 TMR - Node Separation Vdd Triple Redundant Flip/flops D CL R CL K PRE D CL R CL K PRE Q D CL R CL K PRE Q Q voter Q Acceptable Layout - Sequencing of voted F/F s Places redundant elements at greater distance 5/1/

14 Internally Redundant Logic Places redundant nodes in very close proximity - Cell layout critical Isolated Well Transistors* Pshunt IN Pdrive P isolation OUT Dual Data Stream redundant logic** PA PC Vdd Vdd PB Pout PA PC Vdd Vdd PB Pout Nshunt N isolation NA Nout NA Nout Ndrive NC NB NC NB Retargetability Non-standard library cells. Transistors often need sizing to maintain performance. Scalability Adequate separation is critical 5/1/ *Baze, et, al. IEEE NSREC 00, pg 2609 **Wiseman, IEEE Rad. Data Workshop, 94, pg51

15 Internally Redundant Latch Cross Coupled (asymmetric) Redundant state nodes PMOS PMOS PMOS BASIC LATCH PMOS Retargetability / Scalability Requires custom sizing of six transistors with each new process to balance the single node SEU response and achieve adequate hardness 5/1/

16 Internally Redundant Latch DICE* - Dual interlocked storage cell Less sensitive to transistor sizing Table 2. Single Event Effects Test Results ** ** clock data *Calin, et al, IEEE NSREC 96, pg2877 **Alexander, et al. GOMAC 2001 Digest of Papers, pg 257 5/1/

17 Low Power DICE Latch with PRE / CLR Low Power pass gates PRE Clear Preset B1 B2 Q Output buffer D B1 B2 B2 CLR B1 5/1/

18 DICE Latch Layout Restrictions No two same color transistor blocks may be paced side by side PRE B1 B2 Q D B1 B2 B2 CLR B1 5/1/

19 DICE Flip/Flop PRE B2 D B1 B1 B2 Q B1 B2 B2 B2 B1 Retargetability CLR Transistor sizing and pass gate/ logic implementations may need to be traded to optimize speed vs. power Scalability B1 Single node hardness insensitive to transistor sizing. Node separation is critical 5/1/

20 Flip/Flop Comparisons Retargetable / Scalable Flip/Flops in a Single Process POWER (-Q) SPEED (T SH ) HARDNESS* (e/b-d) AREA (µm2) Std Low Power Rise 0.7 µw Fall 0.2 µw Rise 0.21 ns Fall 0.27 ns node 360 Increased I DRIVE Rise 1.0 µw Fall 0.2 µw Rise 0.16 ns Fall 0.15 ns 2x node 460 Low Power triplicate-and-vote Rise 1.72 µw Fall 1.27 µw Rise 0.21 ns Fall 0.27 ns node 1200 DICE Rise 1.4 µw Fall 1.1 µw Rise 0.96 ns Fall 0.97 ns 1.6 x node 520 *preliminary estimates for a proposed SOI process, GEO orbit 5/1/

21 Summary A number of design options exist for improving the SEU hardness of digital logic. However, specific considerations and restrictions must be observed for each technique if these techniques are to be applied over a range of process technologies and reduced feature size. 5/1/