ECSS-Q-HB HANDBOOK Techniques for Radiation Effects Mitigation in ASICs and FPGAs
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1 ECSS-Q-HB HANDBOOK Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernández León Microelectronics Section ESA / ESTEC SEE / MAPLD Workshop May 18-21, 2105
2 OUTLINE Scope and goals of Handbook When and who prepared this Handbook? Classification of mitigation techniques, structure of HB Overview of main chapters (lists of techniques) ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 2
3 Deciphering the handbook coded name Space product assurance (branch Q ) ECSS-Q-HB Handbook EEE Components (discipline 60 ) Techniques for Radiation Effects Mitigation in ASICs and FPGAs ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 3
4 ECSS-Q-HB scope and goals compilation of techniques to mitigate effects of radiation in ASICs & FPGAs techniques grouped according to the different stages (levels) of an IC development flow in addition overview of the space radiation environment and its effects in ICs general guidelines for selecting techniques, how to use the handbook how to validate the mitigation techniques intended users Engineers and IC designers doing selection, use or development of ASIC or FPGA to be used in radiation environment Intended use As guidelines and references only, not requirements ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 4
5 History of ECSS-Q-HB /07: ECSS-Q-ST-60-02: ASIC and FPGA development standard released 2010/03: contract KO to develop 1st ECSS-Q-HB draft : Techniques for Radiation Effects Mitigation in ASICs and FPGAs by TIMA(F) et al. 2010/09: workshop on the topic at ESA/ESTEC 2011/12: Final presentation (version 6 of the HB 1 st draft) with training at ESTEC 2012/02: Final revision to the HB (version 7), with inputs from TIMA & ESTEC 2013/10: ECSS Working Group KO to improve the 1st HB draft for future ECSS public review 2014-today: ECSS Working Group and Secretariat preparing improved HB draft ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 5
6 Who worked in the ECSS-Q-HB-60-02? First HB draft (2012 Q1) put together by TIMA (F), under ESA contract, with key inputs from: M. Alles process and layout level D. Loveless University of Vanderbilt (USA) analogue & mixed-signal circuits M. Nicolaidis R. Velazco TIMA (F) B. Glass European Space Agency (NL) F. L. Kastensmidt Universidade Federal do Rio Grande do Sul (Brazil) digital circuits HB contract manager Digital circuits and FPGAs M. Violante Politecnico di Torino (I) Embedded Software M. Pignol CNES (F) System architecture Final HB version (2015 Q3) by the ECSS WG with inputs/corrections from ESA, Thales, AirbusDS, RUAG, OHB, CNES(F), CERN(CH) and IMEC(B).and anyone interested through Public Review Over 350 citations of industry, academia, vendors and agencies worldwide ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 6
7 classification of mitigation techniques, abstraction levels Outside integrated circuit FPGA Off-chip electronics Software System On Chip Digital, Analogue, Mixed-Signal Electronic System level Inside integrated circuit Digital IP ASIC cell libraries Circuit Architecture level Analogue IP Embedded memories RHBD Physical Layout level Manufacturing Process level RHBP ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 7
8 Handbook table of contents size (pages) chapter # chapter title 1 Scope 10 2 References 3 Terms, definitions and abbreviated terms 5 4 Radiation environment and integrated circuits 2 5 Choosing a design hardening strategy 15 6 Technology selection and process level mitigation 12 7 Layout 29 8 Analogue circuits 22 9 Embedded memories 6 10 Radiation-hardened ASIC libraries Digital Circuits System on a Chip Field Programmable Gate Arrays Software-implemented hardware fault tolerance System architecture Validation methods 33 Annex A Bibliography 3 Annex B Vendor Solutions ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 8
9 Common structure of main chapters a. Overview b. Table of Mit. Techniques vs. Rad Effects c. Mitigation techniques descriptions, with examples, figures Available Test Data (simulations, radiation testing, in-flight) Added value (efficiency) Known issues (Weaknesses, elements to be considered) ID card Abstraction level Pros Cons Mitigated effects Validation Methods Automation tools Vendor solutions ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 9
10 ECSS-Q-HB-60-02: the first chapters 1 Scope 14 2 References 15 3 Terms, definitions and abbreviated terms Terms from other documents Terms specific to the present document Abbreviated terms 18 4 Radiation environment and integrated circuits Radiation environment in space Radiation Effects in ICs Cumulative effects Single Event Effects (SEEs) Non destructive SEE Destructive SEE Summary 28 5 Choosing a device hardening strategy The optimal strategy How to use this handbook 31 ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 10
11 6 Technology selection and process level mitigation 6 Technology selection and process level mitigation 6.1 Overview 6.2 Summary of effects vs mitigation techniques 6.3 Mitigation techniques Epitaxial layers Silicon On Insulator Triple wells Buried layers Dry thermal oxidation Implantation into oxides 6.4 Technology scaling and radiation effects ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 11
12 7 Layout, 8 Analogue circuits 7 Layout Ringed or Enclosed Layout Transistor Contacts and guard rings Dummy transistors Large W/L ratio transistors 8 Analogue circuits Node Separation and Inter-digitation Analogue Redundancy (Averaging) Resistive Decoupling Filtering Modifications in Bandwidth, Gain, Operating Speed, and Current Drive Reduction of Window of Vulnerability Reduction of High Impedance Nodes Differential Design Dual Path Hardening ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 12
13 9 Embedded memories Hardening of individual Memory Cells Resistive hardening Capacitive hardening IBM hardened memory cell HIT hardened memory cell DICE hardened memory cell NASA-Whitaker hardened memory cell NASA-Liu hardened memory cell Bit-interleaving in memory arrays c R Data Scrubbing d /d q R /q 9.4 Comparison between hardened memory cells ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 13
14 10 Radiation-hardened ASIC libraries 10.1 IMEC Design Against Radiation Effects (DARE) 0.18 µm library 10.2 CERN 0.25 µm, 65nm rad hard library 10.3 BAE 0.15 µm rad hard library 10.4 Ramon Chips 0.18 µm and 0.13 µm rad hard libraries 10.5 Aeroflex 600, 250, 130 and 90 nm rad hard libraries 10.6 Atmel MH1RT, ATC18RHA, ATMX150RHA (0.35, 0.18 & 0.15 µm) rad hard lib 10.7 ATK 0.35 µm rad hard cell library 10.8 ST Microelectronics C65SPACE 65nm rad hard library 10.9 RedCat Devices 0.18 µm and 0.13 µm rad hard libraries ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 14
15 11 Digital Circuits b) Combinational logic Clk D Q DFF Voter Spatial redundancy Combinational logic Clk D Q DFF Voter Duplex architectures Triple Modular Redundancy architectures Basic TMR Full TMR Combinational logic Clk D Q DFF Voter Temporal redundancy Triple Temporal Redundancy combined with spatial redundancy Minimal level sensitive latch Fail-Safe, Deadlock-free Finite State Machines Selective use of logic cells ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 15
16 12 System on a Chip Error Correcting Codes Parity check Cyclic Redundancy Check BCH codes Hamming codes SEC-DED codes Reed-Solomon codes Arithmetic codes Low Density Parity Codes Mitigation for Memory Blocks Filtering SET pulses in data paths Watchdog timers TMR in mixed-signal circuits 7 bits of data Number of 1 8-bits including parity bit even odd ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 16
17 13 Field Programmable Gate Arrays Local TMR Global TMR Large grain TMR Embedded user memory TMR Additional Voters in TMR data-paths to minimise DCE Reliability-oriented place and Route Algorithm (RoRA) Embedded processor protection Scrubbing of configuration memory + techniques in Chapters 11 (digital) & 12 (SoC) ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 17
18 14 Software-implemented hardware fault tolerance Redundancy at instruction level Redundancy at task level Redundancy at application level: using a hypervisor ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 18
19 15 System architecture (off-chip) Shielding Watchdog timers Latching current limiters Spatial Redundancy Duplex architectures Lockstep Double Duplex Double Duplex Tolerant to Transients (DT2) Triple Modular Redundancy Error Correcting Codes Off-chip SET filters ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 19
20 TMR variants in this Handbook 11 Digital Circuit s 12 - SoC 13 - FPGA 15 Offchip 3x flip flops 3x combinatorial logic 3x voter Extra voters in data paths Triplets physical layout separated 3x memory blocks comparing analog signals 3x chip Synchronizing logic 3x outputs Basic TMR x x Full TMR x x x x Local TMR x x Global TMR x x x x x Large grain TMR x x x x x x Embedded memory TMR TMR with voters against DCE x x x x x x x Mixed-signal TMR Chip-level TMR x x x x x ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 20
21 16 Validation methods 16.2 Fault injection Fault injection at transistor level Physical level 2D/3D device simulation Transient fault injection simulations at electrical level Fault injection at gate level Fault injection at device level Fault injection in processors Fault injection in FPGAs Analytical methods for predicting effects of soft errors on SRAM-based FPGAs Fault injection at system level 16.3 Real-life radiation tests Tests on-board scientific satellites On-board stratospheric balloons Ground level tests 16.4 Ground accelerated radiation tests Standards and specifications SEE test methodology Static test Dynamic test TID test methodology TID and SEE test facilities Total ionizing dose Single event effects Complementary SEE test strategies Laser beams SEE tests Ion-Microbeam SEE tests Californium-252 and Americium-241 SEE tests SEE tests practical constraints and DUT preparation ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 21
22 Future of ECSS-Q-HB /06: ECSS-Q-HB release for ECSS public review (2 months approx) ==> please check here: to download Handbook during public review and form to submit your feedback! 2015/Q3: ECSS-Q-HB final release as an official new ECSS Handbook ECSS Q-HB Techniques for Radiation Effects Mitigation in ASICs and FPGAs A. Fernandez-Leon SEE/MAPLD 19/05/2015 Slide 22
23 THANKS! Questions? Suggestions? ECSS-Q-HB Handbook Techniques for Radiation Effects Mitigation in ASICs and FPGAs working group convener & book captain SEE / MAPLD Workshop May 18-21, 2105
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