Development of SEU-robust, radiation-tolerant and industry-compatible programmable logic components

Transcription

1 PUBLISHED BY INSTITUTE OF PHYSICS PUBLISHING AND SISSA RECEIVED: August 14, 2007 ACCEPTED: September 19, 2007 PUBLISHED: September 24, 2007 Development of SEU-robust, radiation-tolerant and industry-compatible programmable logic components S. Bonacini, ab K. Kloukinas a and A. Marchioro a a CERN, 1211 Geneva 23, Switzerland b INPG, Grenoble, France sandro.bonacini@cern.ch ABSTRACT: Most of the microelectronics components developed for the first generation of LHC experiments have been defined and designed with very precise experiment-specific goals and are fully optimized for these applications. In an effort to cover the needs for generic programmable components, often needed in the real world, an industry-compatible Programmable Logic Device (PLD) and an industry-compatible Field-Programmable Gate Array (FPGA) are now under development. This effort is targeted to small volume applications or to the cases where small programmable functions are required to fix a system application. The PLD is a fuse-based, 10-input, 8-I/O general architecture device compatible with a popular commercial part, and is fabricated in 0.25 µm CMOS. The FPGA under development is instead a logic block array, equivalent to 25k gates, to be fabricated in 0.13 µm CMOS. The work focusses on the design of SEU-robust registers which can be employed for configuration storage as well as for user data flip-flops. The SEU-robust registers were tested in a heavy-ion beam facility; test results are presented. KEYWORDS: Radiation damage to electronic components; Digital electronic circuits; Front-end electronics for detector readout. Corresponding author. c 2007 IOP Publishing Ltd and SISSA

2 Contents 1. Introduction 1 2. Radiation hardening techniques TID tolerance SEU hardening techniques 3 3. PLD design structure AND array Output Logic PLD chip layout 8 4. FPGA design structure Logic Block Switch matrix architecture 9 5. Experimental results Test procedures Test results Conclusions Introduction The progress in microelectronic technologies applied to programmable logic circuits has allowed to decrease the costs and the development time of digital electronics in the industrial sector as well as in the space and avionics sectors. The use of such devices is also appealing for High Energy Physics (HEP) detectors placed in the vicinity of high-luminosity particle accelerators such as the Large Hadron Collider (LHC). The harsh radiation environment present in these detectors makes Commercial Off-The-Shelf (COTS) components unsuitable for the application and requires the design of custom-designed circuits. The most advanced programmable circuits are Field-Programmable Gate Arrays (FPGAs), which consist of some memory storage banks and a set of logic circuits whose behavior is configured by the content of the memory bank. FPGAs exploit different techniques for the storage of the configuration information. Most commonly SRAMs, FLASH memories and antifuses are used. While the first two allow the user to program the device many times, the latter is One-Time Programmable (OTP). The SRAM-based FPGAs are inherently flexible to meet multiple requirements and offer significant cost and development time advantages. They can be reconfigured after 1

3 the commissioning of the systems to correct errors or to improve performance. SRAM-based FP- GAs can be implemented in standard CMOS processes while FLASH-based FPGAs require special non-volatile processes. Many studies [1] have been done on the radiation effects on commercial FPGAs, proving them to be often sensitive to both Total-Ionizing Dose (TID) and Single-Event Upsets (SEUs). SEUs in FPGAs can occur in the user logic and, in the case of SRAM-based devices, also in the configuration storage. When a configuration cell is corrupted by a particle hit, the user logic can end up being modified, therefore the functionality of the FPGA can be affected and compromised. This latter effect is often referred to as Single- Event Functional Interrupt (SEFI) [2]. SEFIs can also occur when the configuration control state machine of the FPGA enters into an erroneous state. FPGAs are critically sensitive to SEUs due to the large amount of memory elements located in these devices. These must be strongly protected to avoid errors during run time. There are two main techniques to mitigate the SEU radiation effects: introducing redundancy in the Hardware Description Language (HDL) program or cell level architectural hardening. Special constructs in the HDL allow introduction of redundancy in the user logic. These techniques reduce drastically the available circuitry resources of the FPGA and require complex reconfiguration schemes to avoid corruption of the configuration data [3]. Unlike this approach, the objective of our work is the development of programmable circuits where SEU insensitivity is built-in at the storage cell level thus, not requiring the user to exploit any special technique for SEU protection. Programmable Logic Devices (PLDs) are small components which can implement logic functions equivalent to 50 gates. Although PLDs are considered nowadays surpassed by FPGAs, they are still favourable in some applications implementing simple state machines, glue logic circuitry and providing fixes for system design bugs at the late stages of a project. PLDs also suffer from TID. PLDs are in general OTP devices and they are not affected from SEUs in the configuration storage, but the user register can still be corrupted and therefore needs to be protected. This work focuses on the design of an SRAM-based FPGA and a fuse-based PLD that are SEU-robust, radiation-tolerant and industry-compatible. 2. Radiation hardening techniques This section describes the measures taken during the design for the programmable logic circuits to make them radiation-resistant. These are divided into techniques to enhance TID tolerance and strategies to increase SEU robustness. 2.1 TID tolerance Special layout techniques for CMOS technologies were proven to be effective against TID degradation up to the doses required by HEP experiments [4] and a standard cell library in 0.25 µm CMOS commercial technology was designed and qualified [5]. The same layout techniques were employed during the design of our 0.25 µm chips. As suggested by the results published in [6], at least one 0.13 µm CMOS commercial technology does not require special transistor layouts for digital logic in order to be TID-tolerant up to 100 Mrad. In addition, the authors of [6] show that the only requirement to achieve high total dose 2

4 resistance is that all the devices have width bigger than 0.3 µm. This condition is respected in the present work. 2.2 SEU hardening techniques The key point in the design of SEU tolerant programmable circuits is the development of an SEUrobust register which can be used to store the user data as well as the configuration data. In this work, protection of the stored information is achieved by using special circuit techniques in the implementation of the register cells rather than system techniques like Error Correction Coding (ECC), Triple Module Redundancy (TMR) or reconfiguration. The SEU-robust register is made of two identical cascaded latches, the first being the master and the second being the slave. The two latches are a modified version of the Dual Interlocked Cell (DICE), introduced in [7], which is insensitive to single-node particle hits on its memory nodes. The SEU-robust latch is presented in figure 1 and it has 4 memory nodes. These nodes (A,B,C,D) have two stable logic configurations. These are (1,0,1,0) and (0,1,0,1), and any other configuration settles to one of these two states. The circuit topology is such that an SEU on one of the cell s nodes would affect only one of the two nodes immediately connected to it, preserving the data in all nodes. As soon as the charge collection ceases, the unaffected nodes then propagate the correct logic value in the two nodes affected by the upset, making the cell settle to its original state. As can be seen in the figure, the gates of the p-channel transistors are connected to the memory node on their left, and the gates of the n-channel transistors are connected to the memory nodes on their right. It follows that a negative charge collection by a memory node affects only the memory node on its right, while a positive charge collection by a memory node affects only the memory node on its left. Since on each stage the logic value is inverted, no upset can propagate for more than one stage in the same direction. For instance a negative charge collection by node B would propagate to the right through the p-channel transistor which can pull-up node C to a high level, but this does not affect node D; conversely, a positive charge collection by node B would propagate to the left through the n-channel transistor which can pull-down node A, but again this does not affect node D. The original DICE latch has a single local clock buffer. If the clock buffer is upset, the operation of the entire cell is compromised. This upset mechanism is expected to become more pronounced in advanced technologies with smaller feature sizes due to the decrease in capacitance of the circuit nodes. In order to alleviate this upset mechanism, our SEU-robust latch features two independent terminals for the input, output and clock signals, driven by separate signal buffers. Under normal operating conditions, the two inputs are identical. When a particle hits one of the two input (data or clock) buffers, the transient upset will affect only one of the four memory nodes, which are intrinsically immune to this mode of upset. Furthermore, the combinatorial part of the logic can be hit by a particle and generate a Single- Event Transients (SET) [8]. If the logic is fast enough to propagate the induced transient pulse, the SET can appear at the input of the latch following it, where it can be sampled, erroneously, as a valid signal. Whether or not the SET is stored in the latch depends on the temporal relationship between its arrival time and duration, and the falling or rising edge of the clock. A way of protecting the combinatorial part of the circuitry is redundancy, exploiting the double input and double output of the SEU-robust register. The combinatorial blocks can be duplicated, like in figure 2, in such a way 3

5 Figure 1. Fully 2 -redundant SEU-robust latch implemented in this work. The latch has 2 inputs, 2 outputs and 2 local clock buffers. A register is made of two cascaded latches (a master and a slave). Figure 2. Duplicated combinatorial logic style: two independent data paths are created for redundancy. Each one of the two data paths ends driving one input of the SEU-robust register. In turn, each one of the two data paths is fed by one of the two redundant outputs of the previous register stage. Figure 3. Layout view of the SEU-robust register in its 0.13 µm technology version. The figure is divided into the areas which affect the corresponding nodes in the network. The master latch nodes are MA, MB, MC, MD, while the slave latch nodes are SA, SB, SC, SD. By interleaving the master and the slave components the distance among nodes belonging to the same latch is maximized. to have two redundant copies of the logic connected to the two redundant inputs of the flip-flops. In this work, duplication is used where necessary to harden the logic circuitry. As explained above, because of its circuit topology, the latch is intrinsically insensitive to single-node particle hits on its network. Nevertheless, the latch is vulnerable if a particle hits multiple correlated nodes, an event also referred to as multiple-node charge collection. To reduce the probability of this mode of failure we employed a layout topology which increases the distance of the sensitive correlated nodes. To achieve optimal spacing we interleave the nodes of the two latches composing the register, 4

6 since they are independent. Figure 3 depicts the layout of the SEU-robust register. The overall penalty of these techniques is that the logic occupies twice the area of non-seuprotected logic and consumes twice the power. 3. PLD design structure The developed PLD is fully compatible with the commercial 16LV8 component and it has 10 input pads and 8 bidirectional pads. PLDs consist of two sets of logic cells organized in two stages, namely an AND stage and an OR stage. The AND stage performs its operation on the inputs of the PLD creating minterm products that are then summed by the second stage. In a PLD the AND stage is configurable, thus the user can decide which inputs of the PLD participate to each AND, customizing in this way the minterms. The OR stage is hard-wired and not configurable. Figure 4 shows a typical PLD architecture. A configurable Output Logic (OL) containing a register is present at the output of each OR stage. The output of each OL is fed back to the AND array and can be used to form more complex logic. The PLD of this work follows the above mentioned architecture having 8 outputs, 8 minterms per output and 8 logic inputs. Therefore the AND array has 2048 programming bits and the PLD can realize 8 logic functions of 8 minterms formed by the 8 logic inputs and the 8 outputs. Each OL block is connected to a bidirectional pad. Furthermore, in this PLD implementation, each pad connected to the OL blocks can be configured to be input, output or bidirectional, according to the user needs. Two of the PLD inputs are special, since they can be assigned to be the clock and the output enable depending on the configuration, they are fed to all the OL blocks for this purpose. 3.1 AND array The AND array consists in 64 horizontal lines which form the output minterms and 32 vertical lines which bring the inputs from the 8 input pads and from the 8 OL feedbacks in their positive and negated form. A fuse and a transistor are placed at each intersection, and act as the pull-down for the horizontal line connected (see figure 5). If the fuse is burned, the transistor cannot pull down the line, while if the fuse is intact the transistor pulls down the line when its gate input is high. Two pull-up transistors are connected in the middle of each horizontal line. Hence, each horizontal line behaves as a wired NOR of the inputs whose corresponding fuse is intact. The delay of the horizontal line is directly related to the strength of the pull-up and pull-down drivers and to the wiring capacitance of the horizontal line which is about 400 ff. For this reason the drivers should be strong, but, on the other hand, the pull-up cannot be strong since it is always active and it leads to static power consumption when the logic value on the line is low. The size of the pull-up is therefore a trade-off between speed and power consumption. In this work, each horizontal line has two pull-up transistors, a weak primary pull-up and a strong secondary pull-up. The former acts as a keeper with low power consumption, while the latter is activated only when the inputs of the logic change in order to quickly bring the horizontal line to its settling value. This strategy allows having a small static power consumption, due to the 5

7 Figure 4. Typical PLD architecture composed of a configurable AND stage, a fixed OR stage and a set of registers. The empty squares indicate the programmable participation to the AND stage, while the filled squares indicate the fixed participation to the OR stage. Figure 5. Horizontal line with fused pull-downs and primary and secondary pull-up forming an AND. The kick signal drives the secondary pull-up and is activated by the input transition detector. primary pull-up, and a fast response, thanks to the secondary pull-up. A dedicated input transition detector circuit activates the secondary pull-up. Since the configuration of the PLD is stored in fuses, it is intrinsically SEU-hard. The horizontal lines have a high capacitance which is enough to be insensitive to the charge generated by particles with an LET below 25 cm 2 MeV/mg, more than sufficient in the foreseen application. Each horizontal line feeds two inverters which generate two redundant copies of the same wired AND value for the OL, which exploits duplicated logic. The fuses available in the target technology are laser-programmable. One advantage of this type of fuse is a better burned/intact resistance ratio with respect to electrically-programmable fuses. These need a sense amplifier in order to generate a reliable logic level, therefore their area per bit is larger than the one of laser-programmable fuses. Each fuse is composed by a 7 1 µm 2 metal rectangle. In order to allow programming the 6

8 Figure 6. Layout of the fuses in the AND matrix. Each fuse is attached on one side to a short segment which connects it to an horizontal line running on the top or on the bottom. A transistor is placed on the other side of each fuse, acting as a pull-down. The gates are connected in vertical lines. Figure 8. Interlocked buffer. When the inputs of the buffer disagree, the output is unmodified and only when the inputs agree is the output driven to the correct value. Figure 7. Microscope picture of PLD chip. The AND array appears in the center, while the OLs are visible at the rightmost edge of the core. Figure 9. Typical FPGA architecture composed of programmable Logic Blocks (LBs), Input/Output (I/O) elements and a configurable routing mesh. passivation is opened on top of each fuse. Due to layout design rules, the area utilization of a group of 4 fuses is about µm 2. The fuse array occupies 70% of the core area. 3.2 Output Logic Each OL block accepts 8 minterms coming from the AND matrix and is connected to an I/O pad and a second alternate input pad. The behavior of each OL cell depends on 4 configuration bits which decide whether the OL uses the primary pad or the alternate pad and whether it uses it as 7

9 input, output or I/O. The OL blocks are fully duplicated for protection from SETs and the user register is composed by the SEU-robust structure described in section 2.2. The OL feeds back its output value to the AND matrix. The transition between a duplicated domain (the LB) to a non-duplicated domain (the AND matrix) implies a buffering, due to the different capacitance of the lines. The solution adopted in this work is the interlocked buffer, shown in figure 8, which uses the two copies of a duplicated network to make a single buffered line. When the inputs of the buffer disagree the output is unmodified, and only when the inputs agree is the output driven to the correct value [9]. 3.3 PLD chip layout The chip has been fabricated in a CMOS 0.25 µm technology with 3 metal layers. The chip size is 2 2 mm 2, while the core size is approximately µm 2. A picture of the chip is visible in figure FPGA design structure Our target design is an FPGA composed of an array of Logic Blocks (LBs) for an equivalent of 25k gates. To facilitate the development of firmware for the users, our FPGA is topologically fully compatible with an existing commercial component, and therefore it accepts a programming stream almost identical to the one generated by development tools for the corresponding commercial part. The FPGA has 256 configurable I/Os which can be configured as registered or non-registered. The basic element for logic implementation inside an FPGA is a programmable LB that allows the user to implement various logic functions. An LB is usually composed of a configurable combinatorial block which drives a user register. In an FPGA many LBs are interconnected through a two-dimensional mesh of wires with switching elements at wire crossings to configure the routing, like in figure Logic Block The LB in the present work is composed of a 4-input-1-output Look-Up Table (LUT) together with a carry-chain infrastructure and a user register. The diagram of the LB is depicted in figure 10. The LUT can implement any boolean function of 4 variables and holds its truth table in 16 configuration registers. The LUT can also be used as a 16 1-bit RAM block. A special purpose carry-chain logic block eases the implementation of adders, minimizing the number of necessary LBs. Without this structure, the number of LBs used for a n-bit adder would be 2n, since there are 2 outputs per bit, while with this architecture only n LBs are employed. The user register receives the output of the combinatorial part of the LB. An unregistered output is also provided. The user register has asynchronous set and reset signals. A total of 31 configuration bits per LB (including the LUT) are present and are organized in a shift-register structure for configuration loading. The configuration bits as well as the user registers are implemented using the SEU-robust register described in section 2.2. The combinatorial part of the LB is duplicated to protect against SETs. 8

10 Figure 10. Simplified schematic of the Logic Block. A 4-input-1-output LUT generates a user-configured function. A carry chain is provided for an efficient implementation of adders. An user register the output of the combinatorial part of the LB. Figure 11. Periodical structure for the interconnectivity. The block is replicated in 2 dimensions in order to create a large array. Carry-chain connections between LBs are not shown. 4.2 Switch matrix architecture The FPGA interconnectivity is a balanced combination of local connections, which bring signals between neighbouring or close cells, and long connections, which bring signals between distant 9

11 Figure 12. Photograph of the 0.25 µm technology test chip. The test chip is 2 2 mm 2 containing 4 modules of 8 Logic Blocks (LB) each. Figure 13. Photograph of the 0.13 µm technology test chip. The test chip is 2 1 mm 2 containing two types of shift registers; one using our SEU-robust register (9216 registers) and one using a register cell from a commercial standard cell library (4096 registers). places on the chip. A pair of LBs together with its adjacent routing forms a tile, which is the basic structure repeated in two dimensions to form an array. In order to let the user implement a non-congested routing the number of horizontal and vertical programmable routing wires is about the same of the total LB pair I/Os which have to be connected. In this design the number of programmable routing wires is 18 per direction, respectively 6 long lines and 12 short-distance lines. In addition, adjacent tiles share a number of direct connections. Figure 11 depicts the wiring architecture designed. The inputs of each LB pair are physically divided among the four sides of the block in order to distribute their load. Four dedicated clock tree lines are available as a global network coming from dedicated pads. Depending on the length of the lines which they connect and their purpose, the programmable switches are implemented by tristate buffers, transmission gates or multiplexers. 5. Experimental results To assess the performance of the SEU-robust register and measure its effectiveness with respect to the feature size of CMOS technologies, two test chips on, respectively, CMOS 0.25 µm and CMOS 0.13 µm technologies were designed and fabricated. Figure 12 shows the test chip in the 0.25 µm technology. This test chip is 2 2 mm 2, containing 4 modules of 8 Logic Blocks (LB) each. To facilitate SEU characterization, the LBs are configured to implement a shift register of 1,024 registers in total. Figure 13 shows the test chip in the 0.13 µm. The test chip is 2 1 mm 2 containing two types of shift registers; one uses our SEU-robust register and the other uses a register cell from a 10

12 Technology feature size Cell type SEU-robust SEU-robust standard Cell width Cell height Minimum distance between memory nodes n.a. Number of metal levels used Enclosed layout transistors yes no no Minimum device width Typical inverter input capacitance Core power supply voltage Table 1. Comparison between the two tested versions of the SEU-robust register. Units are in µm, ff and V. Figure 14. Results of the heavy-ion beam test on the 0.13 µm technology SEU-robust register. Only the dynamic test showed sensitivity, while no errors were observed for the static test. Error bars representing the upper bound cross section given with 95% confidence level are present where no errors were observed in the dynamic test. commercial standard cell library. Table 1 summarizes the differences between the three implementations. The chips were tested using a heavy-ion beam at the Heavy-ion Irradiation Facility (HIF) in Louvain-La-Neuve, Belgium. 5.1 Test procedures The test setup consisted in a test board placed in the vacuum chamber and connected with a host computer outside the chamber. The test board comprises a socket for the Device Under Test (DUT), a Xilinx Spartan-3 FPGA, a USB interface, some glue logic and linear power regulators. The USB interface is provided for the connection with the host computer, which runs a control program. The 11

13 test board and the software were developed for this application. This program allows a test pattern to be loaded and retrieved via the USB connection to/from the Spartan-3 on-chip memory. The Spartan-3 then applies the test pattern to the DUT, acquires its output signals and compares them with the expected values. All the tests were run at a 25 MHz frequency. Two kinds of tests were performed: a static test and a dynamic test. The static test consists in (a) loading a bit stream in the DUT while the beam is off, (b) exposing the DUT to the beam for a specific fluence and (c) shifting out the stored bit stream and comparing the output bit stream of the DUT with the original. The dynamic test consists instead in continuously writing a bit stream in the DUT while it is exposed to the beam and continuously comparing the output with the original. In both test modes, the SEU cross-sections were derived by dividing the total number of errors observed at each LET by the total fluence of the ion beam. 5.2 Test results The SEU-robust registers fabricated in the CMOS 0.25 µm technology proved to be particularly SEU hard [10]. Experimental data highlighted the SEU insensitivity of the register cell up to an LET of 79.6 cm 2 MeV/mg since no errors were observed in both static and dynamic test modes. At an LET of 112 cm 2 MeV/mg and only in the dynamic test mode, the register cell showed SEU sensitivity, with SEU cross-section of cm 2 /bit. The SEU-robust registers fabricated in the CMOS 0.13 µm technology proved to be SEU immune in the static test mode up to the LET of 37.4 cm 2 MeV/mg, while errors were observed above this LET. In the dynamic test mode the SEU cross-section was measured to be cm 2 /bit at an LET of 32.4 cm 2 MeV/mg demonstrating the higher SEU sensitivity of the 0.13 µm technology with respect to the 0.25 µm technology. The irradiation test results are depicted in figure 14. Experimental data from the irradiation of the shift-register implemented with registers from a commercial standard cell library are also presented for comparison. It is evident that for the SEU-robust register the measured threshold LET is higher while the saturation LET is an order of magnitude lower with respect to the values measured for the commercial library standard cell register. The plots in figure 14 were obtained with three different ions and several tilt angles (in order to achieve a higher LET, proportional to the cosine of the incident angle): Ne 7+ was used for LETs below 10 cm 2 MeV/mg at 0, 45 and 60 tilt; Ar 10+ was used for LETs between 10 and 20 cm 2 MeV/mg, at 0, 45 and 60 tilt; Kr 25+ was used above 20 cm 2 MeV/mg at 0, 30, 45 and 60 tilt. The observed SEU cross section for the SEU-robust register in the dynamic test mode appears to be strongly dependent on the angle of incidence of the beam, suggesting the increased importance of multiple node charge collection phenomena. The LHC environment comprises ionizing particles with LETs up to 17 cm 2 MeV/mg [11]. Hence, from our irradiation test results it is evident that the CMOS 0.25 µm SEU-robust register is suitable to be used as a user register for the PLD circuit. Instead, the implementation of the SEUrobust register in the CMOS 0.13 µm register is suitable only as a configuration register for the FPGA circuit but not as user register where the SEU immunity is found to be compromised in the 12

14 dynamic mode of operation. More effective radiation hardening techniques need to be employed to cover this later purpose. 6. Conclusions An SEU-robust register structure was designed and tested in a CMOS 0.25 µm technology as well as in a CMOS 0.13 µm technology. The SEU-robust register is tailored in order to be used as a memory element in the design of programmable logic circuits. The irradiation test results obtained in the CMOS 0.25 µm technology demonstrate good robustness of the circuit up to an LET of 79.6 cm 2 MeV/mg, which make it suitable for the target environment. The CMOS 0.13 µm circuit instead showed robustness up to an LET of 37.4 cm 2 MeV/mg in the static test mode but had increased sensitivity in the dynamic test mode. The SEU-tolerance in dynamic mode of the 0.13 µm register is sufficient for the implementation of a configuration register but not for a user register, therefore additional strengthening work is necessary. This work demonstrates the feasibility of the design of an SEU-tolerant radiation-hard PLD and an FPGA device. The complete PLD device was fabricated and will soon undergo functional and radiation testing. The design of the LB for the FPGA device in the CMOS 0.13 µm process is now finalized and work is ongoing to complete the interconnection infrastructure. References [1] J. Wang, Radiation effects in FPGAs, in 9th Workshop on Electronics for LHC Experiments, Amsterdam, The Netherlands (2003). [2] R. Koga, Single Event Functional Interrupt (SEFI) Sensitivity in EEPROMs, in Military and Aerospace Programmable Logic Device (MAPLD) International Conference, Greenbelt, Maryland, NASA Goddard Space Flight Center (1998). [3] J. Wang et al., Single event upset and hardening in 0.15 µm antifuse-based field programmable gate array, IEEE Trans. Nucl. Sci. 50 (2003) [4] G. Anelli, Design and characterization of radiation tolerant integrated circuits in deep submicron CMOS technologies for the LHC experiments, PhD thesis, Insitut National Polytechnique de Grenoble, France (2000). [5] K. Kloukinas, F. Faccio, A. Marchioro and P. Moreira, Development of a radiation tolerant 2.0 V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments, in 4th Workshop on electronics for LHC experiments, (Roma), Università di Roma La Sapienza (1998). [6] F. Faccio and G. Cervelli, Radiation-induced edge effects in deep submicron CMOS transistors, IEEE Trans. Nucl. Sci. 52 (2005) [7] T. Calin, M. Nicolaidis and R. Velazco, Upset hardened memory design for submicron CMOS technology, IEEE Trans. Nucl. Sci. 43 (1996) [8] S. Buchner, M. Baze, D. Brown, D. McMorrow and J. Melinger, Comparison of error rates in combinational and sequential logic, IEEE Trans. Nucl. Sci. 44 (1997) [9] R. Shuler, C. Kouba and P. O Neill, SEU performance of TAG based flip-flops, IEEE Trans. Nucl. Sci. 52 (2005)

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