Digital Design: An Embedded Systems Approach Using VHDL
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1 Digital Design: An Embedded Systems Approach Using Chapter 6 Implementation Fabrics Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved. Integrated Circuits Early digital circuits Relays, vacuum tubes, discrete transistors Integrated circuits (ICs, or chips ) Manufacture of multiple transistors and connections on surface of silicon wafer Invented in 1958: Jack Kilby at Texas Instruments (TI) Rapid growth since then, and ongoing Digital Design Chapter 6 Implementation Fabrics 2 1
2 IC Manufacture: Wafers Start with ingot of pure silicon Saw into wafers & polish Early wafers: 50mm Now 300mm Digital Design Chapter 6 Implementation Fabrics 3 IC manufacture: Processing Chemical processing steps based on photolithography Ion implantation Etching a deposited film SiO 2, polysilicon, metal (a) resist film wafer (b) mask (c) (d) (e) Digital Design Chapter 6 Implementation Fabrics 4 2
3 IC Manufacture: Test & Packaging Defects cause some ICs to fail Test to identify which ICs don t work Discard them when wafer is broken into chips Their cost is amortized over working chips Yield depends (in part) on IC area Constrain area to reduce final IC cost Working chips are packaged and tested further Digital Design Chapter 6 Implementation Fabrics 5 Exponential Trends Circuit size and complexity depends on minimum feature size Which depends on manufacturing process Mask resolution, wavelength of light Process nodes (ITRS Roadmap) 350nm (1995), 250nm (1998), 180nm (2000), 130nm (2002), 90nm (2004), 65nm (2007), 45nm (2010), 32nm (2013), 22nm (2016), 16nm (2019) Smaller feature size denser, faster Digital Design Chapter 6 Implementation Fabrics 6 3
4 SSI and MSI In 1964, TI introduced 5400/7400 family of TTL ICs Other manufacturers followed, making 7400 family a de facto standard Small-scale integrated (SSI) 7400: 4 NAND gate 7427: 4 NOR gate 7474: 2 D flip-flop Medium-scale integrated (MSI) 7490: 4-bit counter 7494: 4-bit shift reg Digital Design Chapter 6 Implementation Fabrics 7 Other Logic Families Variations on electrical characteristics 74L : low power 74S : Schottky diodes fast switching 74LS : compromise between speed and power 74ALS : advances low-power Schottky 74F : fast CMOS families 4000 family: very low power, 3 15V 74HC, 74AHC : TTL compatible Digital Design Chapter 6 Implementation Fabrics 8 4
5 Large Scale Integration 1970s: LSI (thousands of transistors) Small microprocessors became feasible Custom LSI chips for high-volume applications SSI/MSI mainly used for glue logic Later additions to 74xx families oriented toward glue-logic and interfacing E.g., multibit tristate drivers, registers Other functions supplanted by PLDs Digital Design Chapter 6 Implementation Fabrics 9 MSI Example: Counter/Display 74LS390: dual decade counter CP0 CP1 MR Q0 Q1 Q2 Q3 74LS08 glue CP0 CP1 MR Q0 Q1 Q2 Q3 CP0 CP1 MR Q0 Q1 Q2 Q3 CP0 CP1 MR Q0 Q1 Q2 Q3 CP0 CP1 MR Q0 Q1 Q2 Q3 74LS47: 7-segment decoder A B C D LT RBI a b c d e f g RBO Digital Design Chapter 6 Implementation Fabrics 10 5
6 MSI Example: Counter/Display +V CP CP0 Q0 CP1 Q1 Q2 MR Q3 A a B b C c D d e +V f LT g RBI RBO +V CP0 Q0 CP1 Q1 Q2 MR Q3 A a B b C c D d e +V f LT g RBI RBO +V CP0 Q0 CP1 Q1 Q2 MR Q3 A a B b C c D d e +V f LT g RBI RBO +V MR CP0 Q0 CP1 Q1 Q2 MR Q3 A a B b C c D d e +V f LT g RBI RBO Digital Design Chapter 6 Implementation Fabrics 11 VLSI and ASICs 1980s: Very Large Scale Integration Then ULSI, then what? VLSI now just means IC design Application-specific ICs (ASICs) Enabled by CAD tools, foundry services Often designed for a range of related products in a market segment Application-specific standard products (ASSPs) E.g., cell phone ICs Digital Design Chapter 6 Implementation Fabrics 12 6
7 ASIC Economics ASIC has lower unit cost than an FPGA But more design/verification effort Higher non-recurring engineering (NRE) cost Amortized over production run ASICs make sense for high volumes Full custom Design each transistor and wire High NRE, but best performance & least area Standard cell Use basic components from a foundry s library Digital Design Chapter 6 Implementation Fabrics 13 Programmable Logic Devices (PLDs) PLDs can be programmed after manufacture to vary their function C.f. fixed-function SSI/MSI ICs and ASICs Higher unit cost than ASIC But lower NRE Ideal for low to medium product volumes Digital Design Chapter 6 Implementation Fabrics 14 7
8 Programmable Array Logic (PALs) Introduced by Monolithic Memories Inc in 1970s First widely-used PLDs Programmed by blowing fusible links in the circuit Use a special programming instrument PAL16L8 16 inputs, 8 active-low outputs PAL16R8 16 inputs, 8 registered outputs Digital Design Chapter 6 Implementation Fabrics 15 PAL16L O1 I2 I1 2 I I8 I10 I1 I2 + I3 I I O8 I9 I10 Digital Design Chapter 6 Implementation Fabrics 16 8
9 PAL16R8 Output Circuit AND array D clk Q Q Feedback path is useful for implementing FSMs Digital Design Chapter 6 Implementation Fabrics 17 Designing with PALs Useful even for simple circuits Single package solution lowers cost Describe function using Boolean equations In HDL, or simple language such as ABEL Synthesize to fuse map file used by programming instrument If design doesn t fit Partition into multiple PALs or use a more complex PLD Digital Design Chapter 6 Implementation Fabrics 18 9
10 8 Digital Design Chapter 6 Implementation Fabrics 24 September 2007 Generic Array Logic (GALs) Programmable AND array OLMC OLMC OLMC OLMC Programmable Output Logic Macrocells (OLMCs) Use EEPROM technology E.g., GAL22V10 D SP AR clk Q Q Digital Design Chapter 6 Implementation Fabrics 19 Complex PLDs (CPLDs) Cramming multiple PALs into an IC Programmable interconnection network Use flash RAM technology to store configuration Interconnection network AND array M/C M/C M/C M/C I/O block Embedded PAL Digital Design Chapter 6 Implementation Fabrics 20 10
11 FPGAs Field Programmable Gate Arrays Smaller logic blocks, embedded SRAM Thousands or millions of equivalent gates RAM RAM RAM Programmable interconnect Digital Design Chapter 6 Implementation Fabrics 21 Logic Block Example Xilinx FPGA Logic Blocks Lookup Tables (LUTs) plus flip-flops E.g., Spartan-II Too complex to program s manually Let synthesis tools map HDL code to s and program the interconnect G4 G3 G2 G1 F5IN BY SR F4 F3 F2 F1 BX CIN CE CLK LUT I4 O I3 I2 I1 LUT I4 O I3 I2 I1 Carry and Control Logic Carry and Control Logic S D Q CE clk R S D Q CE clk R COUT YB Y YQ XB X XQ Digital Design Chapter 6 Implementation Fabrics 22 11
12 I/O Blocks Typically allow for registered or combinational input/output, plus tristates D CE clk D CE clk Q Q V Programmable logic levels, slew rate, input threshold, D CE clk Q Digital Design Chapter 6 Implementation Fabrics 23 Platform FPGAs Include embedded cores for special applications Processor cores Signal processing arithmetic cores Network interface cores Embedded software can run from SRAM in the FPGA Single-chip solution, reduces cost Avoids high NRE of ASIC Digital Design Chapter 6 Implementation Fabrics 24 12
13 Structured ASICs Array of very simple logic elements Not programmable, no programmable interconnect Customized by designing top metal interconnection layer(s) Lower NRE than full ASIC design Performance close to full ASIC May become popular for mid-volume applications Digital Design Chapter 6 Implementation Fabrics 25 IC Packages ICs are encapsulated in protective packages External pins for connected to circuit board Bond-wires or flip-chip connections Digital Design Chapter 6 Implementation Fabrics 26 13
14 Printed Circuit Boards (PCBs) Layers of conducting wires (copper) between insulating material (fiberglass) Manufactured using photolithography and etching Wires interconnect ICs and other components External connections to other system components Digital Design Chapter 6 Implementation Fabrics 27 Through-Hole PCBs IC package pins pass through drilled holes Soldered to PCB wires that join the hole Digital Design Chapter 6 Implementation Fabrics 28 14
15 Surface Mount PCB IC package pins soldered to wires on PCB surface Packages and PCB features are generally smaller than through-hole Digital Design Chapter 6 Implementation Fabrics 29 Multichip Modules (MCMs) Several ICs on a ceramic carrier Can also include thin-film passives and discrete components External connections for PCB mounting Ideal for high-density applications E.g., cell phones Digital Design Chapter 6 Implementation Fabrics 30 15
16 Signal Integrity Signals propagate over bond wires, package pins, PCB traces Various effects cause distortion and noise Signal integrity: minimizing these effects Propagation delay in PCB trace ½c 150mm/ns If two traces differ in length Skew at arrival point can be significant Careful PCB design needed Digital Design Chapter 6 Implementation Fabrics 31 Ground Bounce Transient current flows when an output switches logic level Parasitic inductance causes voltage shift on power supply & ground signals Spikes on other drivers Threshold shift on receivers IC within package +V Bond-wire, lead and PCB inductance Bond-wire, lead and PCB inductance Digital Design Chapter 6 Implementation Fabrics 32 16
17 Minimizing Bounce Bypass capacitors between ground and +V 0.01µF 0.1µF, close to package pins Separate PCB planes for ground and +V Limit output slew rate Trade off against propagation delay high slew rate slew-rate limited signal layer power plane signal layers ground plane signal layer V th Digital Design Chapter 6 Implementation Fabrics 33 Transmission Line Effects Occur when rise time is comparable to path delay Reflections interfere with transitions, resulting in under/overshoot and ringing Can cause false/multiple switching Use PCB layout techniques to overshoot minimize effects ringing 2.5V 2.0V 1.5V 1.0V 0.5V 0.0V undershoot ringing V OH V IH V IL V OL Digital Design Chapter 6 Implementation Fabrics 34 17
18 Electromagnetic Interference Transitions cause electromagnetic fields Energy radiated from PCB traces Induces noise in other systems Subject to regulation Crosstalk Radiation to other traces in the system Particularly adjacent parallel traces PCB layout and slew-rate limiting can minimize both Digital Design Chapter 6 Implementation Fabrics 35 Differential Signaling Reduces susceptibility to noise Transmit a signal (S P ) and negation (S N ) At receiver, sense difference between them S P S N Noise induced on both S P and S N (S P + V Noise ) (S N + V Noise ) = S P S N S S P S N Digital Design Chapter 6 Implementation Fabrics 36 18
19 Summary Exponential improvements in IC manufacturing SSI and MSI TTL logic families ASICs: full-custom and standard cell PALs, CPLDs, FPGAs, platform FPGAs IC packages for PCB assembly Through-hole and surface mount Signal integrity Digital Design Chapter 6 Implementation Fabrics 37 19
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