Engr354: Digital Logic Circuits

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1 Engr354: Digital Logic Circuits Chapter 3: Implementation Technology Curtis Nelson Chapter 3 Overview In this chapter you will learn about: How transistors are used as switches; Integrated circuit technology; Complementary Metal-Oxide-Semiconductor (MOS) logic gates; Programmable Logic Devices. Engr354 Chapter 3

2 Voltage Logic Levels Voltage Logic value V,min Undefined V,max Logic value V SS (Gnd) Voltage Waveforms V x 5% 5% Gnd Propagation delay Propagation delay V A 5% 9% 9% 5% Gnd % % t r t f Engr354 Chapter 3 2

3 Transistors as Switches x = "low" x = "high" (a) A simple switch controlled by the input x Gate Source Drain Substrate (Body) (b) NMOS transistor V G V S V D (c) Simplified symbol for an NMOS transistor Figure 3.2. NMOS transistor as a switch. NMOS and PMOS Transistors V D V D = V V D V G V S = V Closed switch whenv G = Open switch whenv G = V (a) NMOS transistor V S = V G V D V D Open switch whenv G = V D = Closed switch whenv G = V (b) PMOS transistor Figure 3.4. NMOS and PMOS transistors in logic circuits. Engr354 Chapter 3 3

4 Physical Structure of an NMOS Transistor V = G V SiO 2 V = S V V D Substrate (type p) Source (type n) Drain (type n) Structure of a CMOS Circuit Pull-up network (PUN) V f V x V x n Pull-down network (PDN) Engr354 Chapter 3 4

5 CMOS Realization of a NOT Gate T V x V f x T T 2 T 2 on off off on f (a) Circuit (b) Truth table and transistor states CMOS Realization of a NAND Gate T T 2 V f V x T 3 x x 2 T T 2 T 3 T 4 f V x 2 T 4 on on on off off on off off off off on on off on off on (a) Circuit (b) Truth table and transistor states Engr354 Chapter 3 5

6 Programmable Logic Overview How digital circuits are implemented Standard chips; Programmable logic; Programmable logic array (PLA); Programmable array logic (PAL); Complex programmable logic devices (CPLD); Standard cells; Field programmable gate arrays (FPGA); Programming. Custom chips. Standard Chips (a) Dual-inline package Gnd (b) Structure of 74HC4 chip Engr354 Chapter 3 6

7 Implementation of f = x x 2 + x 2 x x x 2 x 3 f Programmable Logic Device as a Black Box Inputs (logic variables) Logic gates and programmable switches Outputs (logic functions) Engr354 Chapter 3 7

8 Structure of a Programmable Logic Array (PLA) x x 2 x n Input buffers and inverters x x x n x n P AND plane P k OR plane f f m Gate-Level Diagram of a PLA x x 2 x 3 Programmable connections P OR plane P2 P3 P4 AND plane f f2 Engr354 Chapter 3 8

9 Example Schematic of a PLA x x 2 x 3 P OR plane P 2 P 3 P 4 AND plane f f 2 PLA and PAL Characteristics Programmable OR and AND planes Hard to fabricate correctly; Reduced speed performance. Led to the development of Programmable Array Logic (PAL) AND plane programmable, OR plane fixed; Simpler to manufacture, less expensive, better performance. Engr354 Chapter 3 9

10 x x 2 x 3 An Example of a PAL P P 2 f P 3 P 4 f 2 AND plane Two Function PAL x x 2 x 3 x 4 P P 2 f P 3 P 4 P 5 f 2 P 6 NOR plane Engr354 Chapter 3

11 PLD Output Logic GAL Generic Array Logic Logic Diagram of the PAL6L8 Engr354 Chapter 3

12 Sequential PLD s 22V Output Logic Macrocells for the 22V Engr354 Chapter 3 2

13 A PLD Programming Unit Plastic Leaded Chip Carrier (PLCC) and Socket Printed circuit board Engr354 Chapter 3 3

14 Pin Grid Array (PGA) Package Complex Programmable Logic Device (CPLD) I/O block PAL-like block PAL-like block I/O block Interconnection wires I/O block PAL-like block PAL-like block I/O block Engr354 Chapter 3 4

15 CPLD Packaging and Programming (a) CPLD in a Quad Flat Pack (QFP) package To computer Printed circuit board (b) JTAG programming Field Programmable Gate Arrays (FPGA) Programmable logic presented so far is good for small circuits 74HC (series in general), a few to s of gates; PLA and PAL, a few hundred gate equivalents; CPLD, a few thousand up to maybe 25K gate equivalents. Need for larger programmable devices Enter FPGA s Do not contain AND and OR planes, rather logic blocks;, up to,, gate equivalents and more on the way. Engr354 Chapter 3 5

16 Structure of an FPGA Logic block Interconnection switches I/O block I/O block I/O block I/O block Logic Blocks are Often Lookup Tables (LUT) x / x 2 / / / f x x 2 f (a) Circuit for a two-input LUT (b) f = x x 2 + x x 2 x f x 2 (c) Storage cell contents in the LUT Engr354 Chapter 3 6

17 A Three-Input LUT x x 2 / / / / / / / / f x 3 Inclusion of a Flip-Flop with a LUT Select In Flip-flop Out In 2 LUT D Q In 3 Clock Engr354 Chapter 3 7

18 Custom Chips Created from scratch; Designer selects number, placement, and connections for each and every transistor; Most dense and highest speed; Requires a substantial design effort; Used only when high performance and density (and maybe secrecy) is required: Like processors or memories. Standard-Cell Chips Gates prebuilt and stored in a library; Gates needed for a design are selected and placed, and wires are routed between them; Standard-cell chips are often called application specific integrated circuits (ASIC s); CAD tools exist to place and route gates. Engr354 Chapter 3 8

19 Gate-Arrays Parts of chip are prefabricated (transistors); Parts of chip are custom fabricated (wires); Provides cost savings since all template wafers are identical; Many variants exist. A Sea-of-Gates Gate Array Engr354 Chapter 3 9

20 Example of a Logic Function in a Gate Array f x x 2 x 3 Programmable Logic Summary How digital circuits are implemented Standard chips; Programmable logic; Programmable logic array (PLA); Programmable array logic (PAL); Complex programmable logic devices (CPLD); Standard cells; Field programmable gate arrays (FPGA); Programming. Custom chips. Engr354 Chapter 3 2

21 Summary In this chapter you learned about: How transistors are used as switches; Integrated circuit technology; Complementary Metal-Oxide-Semiconductor (MOS) logic gates; Programmable Logic Devices (PLD s). Engr354 Chapter 3 2

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