DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N

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1 DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic CONTENTS PART I: THE FABRICS Chapter 1: Introduction (32 pages) 1.1 A Historical Perspective 1.2 Issues in Digiital Integrated Circuit Design 1.3 Quality Metrics of a Digital Design Cost of an Integrated Circuit Functionality and Robustness Performance Power and Energy Consumption 1.4 Summary 1

2 2 CONTENTS 1.5 To Probe Further 1.6 Exercises Chapter 2: The Manufacturing Process (30 pages) 2.1 Introduction 2.2 The CMOS Manufacturing Process 2.3 Design Rules The Contract between Designer and Process Engineer 2.4 Packaging Integrated Circuits 2.5 Perspective Trends in Process Technology 2.6 Summary 2.7 To Probe Further 2.8 Exercises and Design Problems Design Methodology Insert A: Design Layout and Design Rule Verification (6 pages) Chapter 3: The Devices (52 pages) 3.1 Introduction 3.2 The Diode A First Glance at the Diode The Depletion Region Static Behavior Dynamic, or Transient, Behavior The Actual Diode Secondary Effects The SPICE Diode Model 3.3 The MOS(FET) Transistor A First Glance at the Device The MOS Transistor under Static Conditions Dynamic Behavior The Actual MOS Transistor Some Secondary Effects SPICE Models for the MOS Transistor 3.4 A Word on Process Variations 3.5 Perspective: Technology Scaling 3.6 Summary 3.7 To Probe Further 3.8 Exercises and Design Problems Design Methodology Insert B: Device Models and Circuit Simulation (6 pages) Chapter 4: The Wire (40 pages) 4.1 Introduction 4.2 A First Glance 4.3 Interconnect Parameters Capacitance, Resistance, and Inductance Capacitance Resistance Inductance 4.4 Electrical Wire Models

3 CONTENTS The Ideal Wire The Lumped Model The Lumped RC model The Distributed rc Line The Transmission Line 4.5 SPICE Wire Models Distributed rc Lines in SPICE Transmission Line Models in SPICE 4.6 Perspective: A Look into the Future 4.7 Summary 4.8 To Probe Further 4.9 Exercises and Design Problems PART II: A CIRCUIT PERSPECTIVE Chapter 5: The Static CMOS Inverter (47 pages) 5.1 Introduction 5.2 The Static CMOS Inverter An Intuitive Perspective 5.3 Evaluating the Robustness of the CMOS Inverter: The Static Behavior Switching Threshold Noise Margins Robustness Revisited 5.4 Performance of CMOS Inverter: The Dynamic Behavior Computing the Capacitances Propagation Delay: First-Order Analysis Propagation Delay Revisited 5.5 Power, Energy, and Energy-Delay Dynamic Power Consumption Static Consumption Putting It All Together Analyzing Power Consumption Using SPICE 5.6 Perspective: Technology Scaling and its Impact on the Inverter Metrics 5.7 Summary 5.8 To Probe Further 5.9 Exercises and Design Problems Chapter 6: Designing Combinational Logic Gates in CMOS (64 pages) 6.1 Introduction 6.2 Static CMOS Design Complementary CMOS Ratioed Logic Pass-Transistor Logic 6.3 Dynamic CMOS Design Dynamic Logic: Basic Principles Speed and Power Dissipation of Dynamic Logic

4 4 CONTENTS Issues in Dynamic Design Cascading Dynamic Gates 6.4 How to Choose a Logic Style? 6.5 Perspective: Gate Design in the Ultra Deep-Submicorn Era 6.6 Summary 6.7 To Probe Further Design Methodology Insert C: Gate-Level Design and Analysis of Digital Circuits (10 pages) Chapter 7: Designing Sequential Logic Circuits (46 pages) 7.1 Introduction 7.2 Timing Metrics for Sequential Circuits 7.3 Classification of Memory Elements 7.4 Static Latches and Registers The Bistability Principle SR Flip-Flops Multiplexer-Based Latches Master-Slave Based Edge Triggered Register Non-ideal clock signals Low-Voltage Static Latches 7.5 Dynamic Latches and Registers Dynamic Transmission-Gate Based Edge-triggred Registers C2MOS Dynamic Register: A Clock Skew Insensitive Approach True Single-Phase Clocked Register (TSPCR) 7.6 Pulse Registers 7.7 Sense-Amplifier Based Registers (Consolidate with 7.6 under other registers? ) 7.8 Pipelining: An approach to optimize sequential circuits Latch- vs. Register-Based Pipelines NORA-CMOS A Logic Style for Pipelined Structures 7.9 Non-Bistable Sequential Circuits The Schmitt Trigger Monostable Sequential Circuits Oscillators 7.10 Perspective: Choosing a Clocking Strategy 7.11 Summary 7.12 To Probe Further 7.13 Exercises and Design Problems Design Methodology Insert D: Timing Analysis and Verification (8-10 pages) Chapter 8: Dealing with Interconnect (45 pages) 8.1 Introduction 8.2 Capacitive Parasitics Capacitance and Reliability Cross Talk Capacitance and Performance in CMOS

5 CONTENTS Resistive Parasitics Resistance and Reliability Ohmic Voltage Drop Electromigration Resistance and Performance RC Delay 8.4 Inductive Parasitics Inductance and Reliability Voltage Drop Inductance and Performance Transmission Line Effects 8.5 Perspective: When to Consider Interconnect Parasitics 8.6 Chapter Summary 8.7 To Probe Further 8.8 Exercises and Design Problems Design Methodology Insert E: Interconnect modeling and analysis (6 pages) PART III: A SYSTEM PERSPECTIVE Chapter 9: Designing Complex Digital Integrated Circuits (40 pages) 9.1 Introduction 9.2 The Standard-cell Design Approach 9.3 Array-based Design 9.4 Configurable and Reconfigurable Design 9.5 Perspective: Facing the Increasing Design Complexity 9.6 Summary 9.7 To Probe Further 9.8 Exercises and Design Problems Chapter 10: Timing Issues indigitalcircuits (55 pages) 10.1 Introduction - Classification of Timing Approaches 10.2 Synchronous systems Impact of clock variation on performance Clock Distribution Basics Performance and Power Optimization in Synchronous Design Asynchronous Design 10.7.The Asynchronous-synchronous Interface Clock Signal Generation 10.9 Perspective: Alternative Synchronization Approaches Summary To Probe Further Exercises and Design Problems Chapter 11: Designing Arithmetic Building Blocks (50 pages) 9.1 Introduction 9.2 Datapaths in Digital Processor Architectures 9.3 The Adder The Binary Adder: Definitions

6 6 CONTENTS The Full Adder: Circuit Design Considerations The Binary Adder: Logic Design Considerations 9.4 The Multiplier The Multiplier: Definitions The Array Multiplier Other Multiplier Structures 9.5 The Shifter Barrel Shifter Logarithmic Shifter 9.6 Other Arithmetic Operators 9.7 Performance and Power Optimizations in Datapath Structures 9.8 Perspective: Design as a Trade-off 9.9 Summary 9.10 To Probe Further 9.11 Exercises and Design Problems Chapter 12: Designing Memory Arrays (70 pages) 10.1 Introduction 10.2 Semiconductor Memories An Introduction Memory Classification Memory Architectures and Building Blocks 10.3 The Memory Core Read-Only Memories Nonvolatile Read-Write Memories Read-Write Memories (RAM) 10.4 Memory Peripheral Circuitry The Address Decoders Sense Amplifiers Drivers/Buffers Timing and Control 10.5 Memory Reliability and Yield Signal-To-Noise Ratio Memory yield 10.6 Case Studies in Memory Design The Programmable Logic Array (PLA) A 4 Mbit SRAM 10.7 Perspective: Semiconductor Memory Trends and Evolutions 10.8 Summary 10.9 To Probe Further Exercises and Design Problems Design Methodology Insert F: Chip Floorplanning (8 pages) Chapter 13: Connecting to the Outside World (15-20 pages) This also presents mostly new material. It addresses the following topics: - pad design, ESD, guard rings, latchup

7 CONTENTS 7 - off-chip signaling: termination, current versus voltage mode, high-speed serial links, Design Methodology Insert G: Validation and Test of Manufactured Circuits (8 pages) G.1 Test Procedure G.2 Design for Testability G.3 Test-Pattern Generation Problem Solutions Index

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