EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.

Transcription

1 EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries

2 VLSI Design System Specification Functional Design RTL Code (HDL) Synthesis Freq Area Power 64-bit integer multiplier / 1GHz / 0.1mm 2 / 0.1mW C/C++, Verilog, VHDL, module imul_64 (a, b, clk, out64); input a, b, clk; output out64; endmodule Netlist Physical Design Layout Fabrication Bare die Packaging Chip 2

3 From RTL Code to a Chip RTL Code (HDL) 3

4 From RTL Code to a Chip RTL Code (HDL) Synthesis Tech library (e.g., 45nm) Tech-specific logic gates 4

5 From RTL Code to a Chip RTL Code (HDL) Synthesis Physical Design 5

6 From RTL Code to a Chip RTL Code (HDL) Synthesis Physical Design Fabrication 6

7 From RTL Code to a Chip RTL Code (HDL) Synthesis Physical Design Fabrication Packaging 7

8 VLSI Design Full custom ASIC Design Manual Automatic TRs Manually drawn Standard-cell based Placement & Routing Custom Automatic Development time Several months A few days ~ weeks 8

9 Standard-Cell-Based Design Provides good performance low power small area Other design styles FPGA PLA 9

10 Standard-Cell-Based Design Standard cells A set of logic gates Have the same height. Width varies. Pre-characterized for timing and power analysis. INV NAND2 10

11 Standard Cells (Layout) in out in1 in2 out VDD VDD n+ (n-implant) n-well p-well p-well n-well p+ (p-implant) contact poly (gate) in out in1 in2 metal 1 out cell bounrary p-well n-well p-well n-well GND GND INV NAND2 11

12 Standard Cells (Layout) M3 VDD n-well p-well M2 M1 in GND p-well out n-well p+ n+ n+ p+ p+ n+ n-well p-epi substrate Top-down view Side view 12

13 Design Rules VDD n-well p-well : Min. distance (poly, contact) 2: Min. distance (metal 1) : Min. distance (p-active, n-well boundary) in out 4: Min. width (poly) 5: Min. width (metal 1) 6: Min. distance (contact) 7: Min. distance (contact, n-well bounrary) p-well n-well 6 GND 13

14 Standard Cells (Layout) in out in1 in2 out VDD VDD n+ (n-implant) n-well p-well p-well n-well p+ (p-implant) contact poly (gate) in out in1 in2 metal 1 out cell bounrary p-well n-well p-well n-well GND GND INV NAND2 14

15 Standard Cells (Abstract) in out in1 in2 out VDD VDD metal 1 cell bounrary in out in1 out in2 GND GND INV NAND2 15

16 Standard-Cell-Based Design in1 in2 out in out VDD VDD metal 1 in out in1 in2 cell bounrary out via12 GND GND metal 2 in1 out in2 in out VDD 16

17 Standard-Cell-Based Design Deal with Standard cells (pre-drawn and pre-characterized) Routing layers (M1, via12, M2, via23, ) 17

18 Standard-Cell-Based Design Intellectual Property (IP) blocks Pre-created blocks Memory Arithmetic Cryptographic DSP Controller 18

19 Standard-Cell-Based Design Macro Standard cells I/O cell 19

20 Delay Calculation & Timing Analysis Pre-characterized cells Index_2 Input transition (ns) Output capacitance (ff) 3 rd 5 th Index_1 Delay (29ps) 20

21 Delay Calculation Interconnect delay l t modeling w s RR = ρρ ll tt ww CC = εε tt ll ss DDDDDDDDDD RRRR ll 2 21

22 Timing Analysis d4 d1 d5 d6 d2 d7 d8 d3 d10 d9 d11 d12 d13 22

23 Standard-Cell-Based Design What should we do? Find the locations of the macros. Find the locations of the standard cells. Route the macros and the standard cells. Power/ground Signal Clock Bus Extract parasitic RC. Analyze the final layout. Timing (clock frequency) Power consumption (dynamic / leakage) Area Power integrity Signal integrity Thermal 23

24 Standard-Cell-Based Design Floorplanning (macro placement) Placement (standard cell placement) Pre-CTS optimization Clock-Tree Synthesis (CTS) Post-CTS optimization Routing Post-routing optimization 24

25 Layout (GDSII stream format) Foundry (Semiconductor manufacturing) TSMC, Global Foundries, Bare dies 25

26 Input Layout (GDSII stream format) A set of geometric objects VDD 2 in 1 n-well out p-well 1: Layer id 3, polygon { 50, 40, 70, 40, 70, 220, 50, 220, 50, 140, 20, 140, 20, 110, 50, 110, 50, 40 } 2: Layer id 7, rectangle { 10, 105, 40, 150 } p-well n-well GND 26

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28 M3 M2 M1 p+ n+ n+ p+ p+ n+ n-well p-epi substrate 28

29 p-epi p+ substrate 29

30 SiO 2 p-epi p+ substrate Gate-oxide deposition 30

31 SiO 2 p-epi p+ substrate Photoresist 31

32 SiO 2 p-epi p+ substrate Mask 32

33 SiO 2 p-epi p+ substrate Expose (photolithography) 33

34 SiO 2 p-epi p+ substrate After photolithography 34

35 SiO 2 p-epi p+ substrate Remove mask 35

36 p-epi p+ substrate Etching 36

37 p-epi p+ substrate Etching 37

38 p-epi p+ substrate Oxide deposition 38

39 p-epi p+ substrate Photoresist 39

40 p-epi p+ substrate Mask 40

41 p-epi p+ substrate Photolithography 41

42 p-epi p+ substrate After photolithography 42

43 p-epi p+ substrate Etch 43

44 p+ (p-well) p-epi p+ substrate Doping 44

45 n+ (n-well) p+ (p-well) p-epi p+ substrate Doping 45

46 n+ (n-well) p+ (p-well) p-epi p+ substrate Poly 46

47 n+ (n-well) p+ (p-well) p-epi p+ substrate Etch 47

48 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Doping 48

49 SiO 2 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Oxide deposition 49

50 contact SiO 2 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Contact 50

51 contact SiO 2 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Metal 1 51

52 contact SiO 2 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Via12 52

53 p-epi p+ substrate Chemical-mechanical-polishing (CMP) 53

54 54