ECE 172 Digital Systems. Chapter 2 Digital Hardware. Herbert G. Mayer, PSU Status 6/30/2018
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1 ECE 172 Digital Systems Chapter 2 Digital Hardware Herbert G. Mayer, PSU Status 6/30/2018 1
2 Syllabus l Term Sharing l Standard Forms l Hazards l Decoders l PLA vs. PAL l PROM l Bibliography 2
3 Product Term Sharing x 1 x 2 x 3 x 4 f 1 f 2 3
4 Product Term Sharing May Result in K-Maps Different from Optimizing f1 and f2 separately 4
5 Product Term Sharing Students figure out f1 and f2 in class: Group as many 1-s together as possible Never mind if some 1-s get covered repeatedly Also look across the board s boundary for grouping 1-s Ditto if you are grouping 0-s Now find f1 and f2! Also named F1 and F2 5
6 Product Term Sharing 6
7 Circuit for Product Term Sharing 7 7 7
8 Product Term Sharing 8
9 K-Maps in Gray Code Drawing K-Maps in Gray Code: Remember Gray Code rule: 1 single variable changes from n -> n+1 K-Map must be constructed correctly So adjacent cells differ in only one variable K-Map must be plotted correctly Minterms from truth table or compact form Minterms from partially reduced expressions K-Map must be circled correctly Remember that K-Maps wrap at edges Can be viewed as tube, or even as torus 9
10 Other Uses of Gray Code Mechanical 8-Bit Gray Code Rotary Encoder 10
11 Standard Forms 11
12 Vertical Layout Scheme SOP Form 12 12
13 Vertical Layout Scheme SOP Form 13
14 Gates With 2 Inputs Solution when 3 inputs needed: Cascading gates 14
15 Vertical Layout Scheme POS Form 15
16 Vertical Layout Scheme POS Form F2 = (X+Y) (X+Y) (X+Z) 16
17 Hazard Examples 17
18 Dynamic Hazards Dynamic hazards occur in multi-level circuits with multiple paths, each having different delays from input to output Do not occur in 2-level SOP (or POS) designs Requires these further timing choices, each with differing timings, to cause multiple glitches 18
19 Hazard Exercise1 Using And-, Nand-, and OR gates, and inverters Gate inputs or outputs may also be inverted internally, via inversion bubbles directly at input or output pins Build circuit F( A, B, C, D ) = B D + ABC + ACD Step 1: Draw circuit for function of 4 variables F( A, B, C, D ) = B D + ABC + ACD in SoP form No need to minimize We ll use same circuit in Step 2 19
20 Hazard Exercise1 Solution to Step 1; other solutions possible: Circuit for F( A, B, C, D ) = B D + ABC + ACD in SoP form 20
21 Hazard Exercise1 Step 2: Using function F( A, B, C, D ) = B D + ABC + ACD, draw the Karnaugh map for F() Identify where static hazards can occur Add terms to remove these hazards and design a new hazard-free logic function HF() 21
22 Hazard Exercise1 Hazards for F() = B D + ABC + ACD can occur at color marked boundaries To be added: AC D + ABD + AB C!!!! C! C!!!! 1! 0! 0! 1!!!!! 0! 0! 0! 0! B!!! A! 1! 1! 1! 0! B!! A! 1! 0! 1! 1!! D! D!!!!! Karnaugh!Map!Circuit!F()!!!! Hazards!marked!in!colors! 22
23 Hazard Exercise1 So hazard free function HF( A, B, C, D ) = B D + ABC + ACD + AC D + ABD + AB C 23
24 Hazard Examples Hazards " Outside Electrical Engineering 24
25 Hazard Exercise2 Explain static-1 hazard in sum-ofproducts circuit: What causes such a hazard? Will a correctly designed two-level circuit have static-1 hazards? How can such hazards be prevented? Which (almost) synonym for hazard is used colloquially, though incorrectly? 25
26 Hazard Exercise2 Explain static-1 hazard in sum-of-products circuit: What causes such a hazard? Different propagation delays through circuit by paths of differing lengths Will a correctly designed two-level circuit have static-1 hazards? No, because all paths have same timing How can static-1 hazards be prevented? By adding further circuitry that solves the timing difference via additional steps in paths; name: consensus path Which (almost) synonym for hazard is used colloquially? Glitch, but keep in mind they are different! Glitch is actual occurrence 26
27 Hazard Exercise3 Question1: Explain the term dynamic hazard in a two-level sum-of-products circuit Question2: Can they occur in two-level SoP circuit? 27
28 Hazard Exercise3 Question1: Explain the term dynamic hazard in a two-level sum-of-products circuit Answer1: A dynamic hazard is the repeated change of the output signal caused by a single change of one of the input signals. Happens, when there are multiple paths to the output signal, but each with different delays Question2: Can they occur in two-level SoP circuit? Answer2: Cannot occur in two-level SoP, because all delay levels are the same, namely 2! 28
29 Hazard Exercise4 Problem definition: Given function f7() of 4 variables f7( w, x, y, z ) = xy + wy + w x z, draw its Karnaugh map! Identify, static-1 Hazards Compute consensus terms, and add these terms, so the new f7_free( w, x, y, z ) circuit is hazard free! 29
30 Hazard Exercise4 Function f7( w, x, y, z ) = xy + wy + w x z, with Karnaugh map. Now find hazard locations, by analyzing map of f7(): y! y!!! 0!! 1!! 1! 0!!!! 1! 1! 0! 0! x!! w! 1! 1! 1! 1! x! w! 0! 0! 1! 1! z! z!!! Function!in!f7()!!!! 30
31 Hazard Exercise4 Hazard places are labeled blue (extending to 4 cells in order to minimize terms), yellow (across 4*4 Karnaugh fields), and green These are the products: w y z + wx + x yz f7_free() = xy + wy + x w z + w y z + wx + x yz will be free of hazards; notice: more complete! 31
32 Hazard Exercise5 Given the K-Map for function K( a, b, c, d ) below, express K() as a Boolean function in SoP form Identify where hazards can occur Devise a hazard-free function K_free( a, b, c, d ) that is functionally equivalent to K()
33 Hazard Exercise5 Boolean function: K( a, b, c, d ) = a d + a b c 33
34 Hazard Exercise5 Identified hazard locations for K() Marked in blue: 34
35 Hazard Exercise5 Added term b c d to K() to form K_free() Consensus term: b c d K_free() = K() + b c d = a d + a b c + b c d 35
36 Decoders 36
37 Decoders n-to-2 n decoder Convert n=2 input lines to one of 2 n = 4 output lines When decoder has EN enabled, is referred to as demultiplexer (dmux). EN is often active low Students soon design electric circuit in class! 37
38 Decoders Y0 = I0 I1 Y1 = I0 I1 Y2 = I0 I1 Y3 = I0 I1 Students design electric circuit for Y0.. Y3 now: 4 output signals Y0.. Y3. Use 2-input and-gates, ignore EN 38
39 Decoders Converts binary code on n = 2 input lines to one of 2 n = 4 output lines; But EN ignored here! I1 I0 Y0 Y1 Y2 Y3 39
40 Decoders with EN Y0 = EN I0 I1 Y1 = EN I0 I1 Y2 = EN I0 I1 Y3 = EN I0 I1 40
41 Decoders Map binary code of n input lines to exactly 1 of 2 n output lines EN I1 I0 With EN signal in circuit, which is EN negated, then: EN = EN Y0 Y1 Y2 41 Y3 41
42 Decoders Sometimes outputs are active low! (EN ignored here) B 1 B 0 F 0 F 1 F 2 F F0 F1 F2 F3 42
43 Decoders Students verify correctness of 5 random active-low cases: 1. F 0 = 0, if B 1 and B 0 2. F 1 = 1, if B 1 and B 0 B 1 B 0 F 0 F 1 F 2 F F 2 = 1, if B 1 and B 0 4. F 3 = 0, if B 1 and B 0 5. F 3 = 1, if B 1 and B 0 F 0 F 1 F 2 F 3 43
44 Decoders Bubble matching is applicable, when for a given logic function F() a type of gate is used that is different from what F() requires E.g. logical and gates are used, yet only nand gates are available, so nands are used instead To keep F() invariant, negater is inserted in path of negated and To be applied to all inputs That is matching a bubble that serendipitously popped up, with another one, to offset its logic inversion 44
45 Decoders When using decoders with active low outputs, use bubble matching to use correct gate Example: Implement XNOR with DMUX F = X Y = F( X, Y) = (0,3) X Y X# #Y not(#x #Y#)
46 Decoders Decoders in Bletchley Park, England, WW2 46
47 Fuses Fuses were actual (real) fuses in early technology, now they generally are not fuses; --just still called fuses: Can be: fuses, transistor circuits, or SRAM-based Volatile and nonvolatile: Nonvolatile UV (ultra-violet erasable) EE (electrically erasable) Universal Programming Unit (from manufacturer) Fuse map JEDEC standard format (Joint Electronics Device Engineering Council) Several programs generate (MACHXL, ABEL, CUPL) 47 47
48 Programmable Logic Devices 48
49 PLD Implementation PROM Schematic Capture PLA PAL/GAL CPLDs Design Tools Fuse Map HDL Tool and PLD vendors: Xilinx, Altera, Lattice 49 Universal Programmer
50 PROMs 50 50
51 PAL vs. PLA PLAs and PALs are both programmable logic devices that implement combinadonal circuits PLA has a programmable and-gate array, and a programmable or-gate array PAL has a programmable and-gate array, and a fixed or-gate array (newer, yet more restricted) As a result, PLAs are slower (longer path), harder to implement, and more expensive (more silicon real-estate) Detail on both below... 51
52 PLAs Programmable logic arrays (PLA) are PLD used to implement a specific combinational circuits PLA consists of and-gate planes with 2 n and-gates for n inputs Linked to or-gate planes producing output signals There are m outputs Allows generation of sums of products of input signals PLA differs from PAL by allowing both and- and or-gate planes to be programmable! 52
53 Generic PLAs 53
54 PLA 54
55 PAL Programmable arrays logic (PAL) is a technology used to implement logic functions Introduced 1978 by Monolithics Memories Inc. (MMI); now Lattice semiconductors OR MMI trademarked the term PAL PALs consist of small PROMs plus added output logic to implement any desired logic function Using specialized machines, PAL devices were field-programmable, i.e. customer lab 55
56 PAL PAL comes in several variants: One-time programmable (OTP) devices could not be updated after initial programming MMI offered a similar family called HAL, or "hard array logic", which were like PAL devices maskprogrammed at factory UV erasable versions had a quartz window over the chip die and could be erased for re-use with an ultraviolet light source; like EPROMs Later versions (e.g.: PALCE22V10) were flash erasable devices 56
57 PAL Flash Erasable: type of non-volatile storage device (similar to EE Prom) where erasing must be done by block Rather than by individual datum Superseded in late 1990 by FEPROMs that could be re-written, some fixed but large number of times 57
58 PALs & GALs 58
59 PAL Function Sharing, Added Input 59
60 Advantages to PLDs Shorten design Ome n Rapid prototyping! Rapid design changes n Reprogrammable l No masks, jumpers, PCB traces Decrease PCB real estate n Less space than mulople standard logic packages Improve reliability n Fewer packages, fewer external interconnects 60
61 PALxxyyzz Nomenclature xx Maximum number of AND array inputs zz Maximum number of dedicated outputs y Type of outputs Combinational H active high L active low P programmable C complementary R registered RPregistered, with programmable polarity V Versatile: programmable 61
62 Nomenclature Samples PAL3H2 3 inputs 2 outputs Active H outputs PAL16L8 16 inputs 8 outputs Active L (0-s of function) PAL22V10 22 inputs 10 outputs Active L or H (1-s or 0-s) Registered if desired 62
63 PAL 63 63
64 GAL Emulate any PAL Reprogrammable Fuses are non-volatile memory cells 64 64
65 CPLDs Complex PLDs 65
66 Designing with PROMs A B C F Address Data C B A F XXXXXXX XXXXXXX XXXXXXX XXXXXXX XXXXXXX XXXXXXX XXXXXXX XXXXXXX 66
67 Example Implement: F1 = inverter of A (NOT A) F2 = OR gate F3 = NAND gate F4 = XOR gate With: a PROM a PLA a PAL A B F1 F2 F3 F
68 PROM Implementation NOT, OR, NAND, XOR A B F1 F2 F3 F Fuse Map Address Data 0 A 1 F
69 PLA Implementation NOT, OR, NAND, XOR A B F1 F2 F3 F
70 PLA Implementation NOT, OR, NAND, XOR A B F1 F2 F3 F
71 PAL Implementation NOT, OR, NAND, XOR A B F1 F2 F3 F
72 Bibliography 1. M. Morris Mano et al: Logic and Computer Design Fundamentals, 2016 Pearson, ISBN-10: Shen, John Paul, and Mikko H. Lipasti: Modern Processor Design, Fundamentals of Superscalar Processors, McGraw Hill,
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