Combinational Logic. Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations

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2 Combinational Logic Design Process 1. Capture the behavior 1. Original can be in the form of a truth table or equations ɢɢɢɢɢɢɢ 2. Convert to equations 3. Simplify if possible Using boolean algebra More complex methods will be presented later 2. Convert the behavior to a circuit

3 Combinational Logic Design Process Example Using the following truth table Determine the canonical sum of products equation Simplify the equation Draw the circuit ʺ챆 ɢ ABC F

4 Reverse Engineering a Circuit Just as you can create a circuit from an equation, you can create an equation from a circuit ɢ渚 ɢ Start at the output and work backwards This can be useful when optimizing a design trying to understand someone else s work.

5 Reverse Engineering Example Determine the equation for the following circuit: C B A ʺɢɢ NOT AND3 OR Z NOT AND3 NOT

6 More Complex Gates Three-State Buffer Decoder Encoder Multiplexer (Mux) Demux نɢ

7 Buffers A buffer is like an inverter, but does not invert the signal Buffers strengthen a signal to remove loss Can also be used to change between signal levels i.e. from a 3.3V HIGH to a 5V HIGH ʺɢɢ Three state buffers are special buffers that can drive a signal HIGH or LOW, but also to a third high impedance (aka. High Z) state to prevent the output from being driven. This allows for multiple circuits to drive a single output, BUT ONLY ONE AT A TIME. Multiple buffers driving an output may fight each other.

8 Three State Buffer F = A EN EN EN A F A F 0 0 Z ɢቆ 0 1 Z Note: Any design using 3 state buffers must ensure that ONLY ONE buffer is driving the bus at a time.

9 Decoder Generally speaking, decoders are multiple input and multiple output devices that convert an input code into a different output code. ʺɢ鸀 Ϙ We will examine a binary decoder Binary Decoder converts n bit number to a 2 n output where only the output whose number matches the input code is a 1. All other outputs are 0. Can be thought of as a minterm or maxterm generator.

10 Simple 1:2 Binary Decoder If the input bit (I) is 0, output D0 is 1 NOT D0 output D1 is 0. If the input bit (I) is 1, ɢṆ I D1 output D0 is 0 output D1 is 1. I D1 D0

11 2:4 Decoder with Enable EN I1 I0 NOT NOT NOT NOT AND AND AND AND D0 = EN * I1' * I0' ʺɢ쿰Ϙ D1 = EN * I1' * I0 Most decoders contain an enabling input to allow or prevent a signal to pass AND AND AND AND D2 = EN * I1 * I0' D3 = EN * I1 * I0 When EN = 0, all outputs are 0

12 Using Decoders as Minterm Generators Any POS or SOP function can be implemented with a decoder Each input code corresponds with a line of the truth table. To implement a SOP, OR all decoder outputs that correspond with a 1 output in the truth table To implement a POS, negate the outputs that correspond with a 0 in the truth table and AND them together. Example: Using an 8 output decoder, implement the function F = ABC + AB C + A B C F = SUM(7, 5, 1) A B C I2 I1 I0 D7 D6 D5 D4 D3 3:8 Decoder OR3 F D2 D1 D0 Example 2: Using an 8 output decoder, implement the function F = (A +B +C) (A +B+C ) (A+B+C ) (A+B+C) By inverting all of the outputs, the decoder is made into a maxterm generator

13 Binary Decoder Questions How many output bits would be required for a binary decoder with 4 inputs? ʺ 鯰 Ϩ If the previously mentioned decoders input is set to 0101, what would the outputs be set to?

14 Encoder An encoder has the opposite function of a decoder. In general, encoders and decoders do the same thing convert one code to another. Decoders generally have more outputs than inputs. ɢマルク Encoders generally have fewer outputs than inputs. In the case of a binary encoder, a 2 n bit input code is converted to an n bit output code We assume that only one input is equal to 1 at a given time. What would happen if more than one input were 1? To solve this situation, we use priority encoders

15 Priority Encoder Priority encoders handle the case where more than one input is a 1 by assigning a priority to each input. The highest priority input with a 1 is treated as if it is the only input that is set to 1. ʺ D7 D6 D5 D4 D3 D2 D1 D0 E2 E1 E0

16 Priority Encoder Questions If a priority encoder has 32 inputs, how many outputs are required? ɢ 㽆 If an encoder has inputs I0 through I31, with the higher numbered input having higher priority, what would the output be if I8 = I4 = 1 and all other inputs are equal to 0?

17 Multiplexer Multiplexers are digital switches that select 1 of N inputs to be assigned to a single output. The value of the binary select signal determines which numbed input has it s value provided at the output. Often called a Mux A Mux can be implemented using standard gates or decoders combined with 3 state buffers ʺᑆ I3 I2 I1 I0 S1 S0 D S1 S0 D 0 0 I0 0 1 I1 1 0 I2 1 1 I3

18 Multiplexer Implementations 2:1 Mux 4:1 Mux I3 AND3 I1 I0 AND OR D ɢ 䡆 I2 I1 AND3 OR4 D S NOT AND AND3 I0 AND3 S1 NOT S0 NOT

19 4:1 Mux using Decoders and 3 State Buffers S1 S0 I1 I0 D3 D2 2:4 Decoder D1 D0 I3 ʺ I2 D I1 I0

20 Multiplexer examples How many select bits are required for a 8:1 mux? ɢ 呆 What is the output value of a mux that has inputs I15 (MSB) through I0 with the input value 0xB15F the select signal is set to 0x5? Build a 4:1 mux using 2:1 muxes.

21 Implementing simple functions with Multiplexers Muxes can also be used to implement simple logic functions Use function input bits as selects Wire MUX inputs to the ɢʘ output values of the truth table. Example 1: Implement the function F = A + B using a 4:1 mux Example: Implement the function F = A B + B C

22 Demultiplexer A Demultiplexer implements the opposite functionality of a Mux 1:M demux takes the one input value and assigns it to the output determined by the select signal. All other outputs are 0. 원 Ϝ I S0 S1 D3 D2 D1 D0

23 Active Low Inputs So far we have considered circuits that are active HIGH (logic 1) The circuit is considered to be turned on and doing it s intended purpose when the input is HIGH It is also possible to use negative logic with active low inputs The circuit is considered to be turned on and doing it s intended purpose when the input is LOW. Active low inputs are indicated by the use of an inversion bubble. 원 Ϝ I2 D7 I1 D6 I0 D5 D4 D3 D2 D1 D0 Active LOW decoder

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 6 (31 Jan 2008) 1 Announcement 2 1 Reminder A logic circuit is composed of: Inputs Outputs Functional specification