8.1. Unit 8. Fundamental Digital Building Blocks: Decoders & Multiplexers
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1 8. Unit 8 Fundamental Digital Building Blocks: Decoders & Multiplexers
2 8.2 Checkers / Decoders Recall AND gates output '' for only a single combination OR gates output '' for only a single combination Inputs (inverted or non-inverted) determine which combination is checked for We say that gate is "checking for" or "decoding" a specific combination x y z AND gate decoding (checking for) combination F X Z F x y z OR gate decoding (checking for) combination F X Z F
3 8.3 Motivation Just like there are patterns and structures that occur commonly in nature, there are several common logic structures that occur over and over again in digital circuits Decoders, Muxes, Adders, Registers In addition, we design hardware using a hierarchical approach We design a small component using basic logic gates (e.g. a -bit mux) We build a large component by interconnecting many copies of the small component + a few extra gates (e.g. a 32-bit mux) We build chips by interconnecting many large components (e.g. a router) Each components is truly made out of many gates but we the design process is faster and easier by using hierarchy Let's look at a few common components We'll start by describing the behavior of the component and then determine what gates are inside
4 DECODER 8.4
5 8.5 Decoders A decoder is a building block that: Takes in an n-bit binary number as input Decodes that binary number and activates the corresponding output Individual outputs for ALL 2 n input combinations 3-to-8 Decoder There are gates inside to implement each output D D 3-bit binary number Z (LB) X (MB) D2 D3 D4 D5 output for each combination of the input number D6 D7
6 8.6 Decoders A decoder is a building block that: Takes a binary number as input Decodes that binary number and activates the corresponding output Put in 6=, Output 6 activates ( ) Put in 5=, Output 5 activates ( ) Binary #6 Z (LB) X (MB) D D D2 D3 D4 D5 D6 D7 Only that numbered output is activated
7 8.7 Decoders A decoder is a building block that: Takes a binary number as input Decodes that binary number and activates the corresponding output Put in 6=, Output 6 activates ( ) Put in 5=, Output 5 activates ( ) X Z D D D 2 D 3 D 4 D 5 D 6 D 7 Binary #5 Z (LB) X (MB) D D D2 D3 D4 D5 D6 D7 Only that numbered output is activated
8 8.8 Decoder izes A decoder w/ an n-bit input has 2 n outputs output for every combination of the n-bit input D D D2 X (MB) D3 n inputs (2) 2-to-4 Decoder 2 n outputs (4) n inputs (3) A A A2 (MB) to-8 Decoder 2 n outputs (8)
9 8.9 Exercise Complete the design of a 2-to-4 decoder X D D D2 D3 X (MB) D D D2 D3 D y D x D2 D3
10 8. Building Decoders 3-bit number [A2:A] Checker for Checker for Checker for Checker for Checker for Checker for O O O2 O3 O4 O5 A A A2 O O O2 O3 O4 O5 Checker for O6 O6 Checker for O7 O7
11 8. Vending Machine Example Assuming the keypad produces a 4-bit numeric output, add logic to produce the release signals for each of the 6 vending items A[3:] 4-to-6 decoder Consider any problems with this design.
12 8.2 Enables In a normal decoder exactly one output is active at all times It may be undesirable to always have an active output We can add an extra input (called an enable) that can independently force all the outputs to their inactive values X (MB) D D D2 D3 One output will always be active X (MB) E D D D2 D3 2-to-4 Decoder Enable Will force all outputs to when E = (i.e. not enabled)
13 8.3 Enables When E=, inputs is ignored X Enable (MB) E D D D2 D3 ince E=, all outputs = When E=, inputs will cause the appropriate output to go active X Enable (MB) E D D D2 D3 ince E=, outputs will function normally
14 8.4 Enables Enables can be implemented by connecting it to each AND gate of the decoder A A B B A D D (MB) B D2 D3 E When E=, AND anything = When E=, AND anything = that anything, which was the normal decoding logic
15 8.5 Multiplexers Multiplexers are one of the most common digital circuits Anatomy: n data inputs, log 2 n select bits, output A multiplexer ( mux for short) selects one data input and passes it to the output 4-to- Mux i n data inputs i i i2 i3 y output i i2 I3 s log 2 n select bits
16 8.6 Multiplexers 4-to- Mux 2 Thus, input 2 = C is selected and passed to the output A B C D i i i2 i3 s elect bits = 2 = 2. y C i i i2 I3 As long as the select bits are 2 = 2, whatever bit value appears on input 2 is copied to the output, same as if we had just wired input 2 directly to the output.
17 8.7 Multiplexers 4-to- Mux 2 Thus, input = A is selected and passed to the output A B C D i i i2 i3 s elect bits = 2 =. y A i i i2 I3
18 8.8 Exercise: Build a 4-to- mux Complete the 4-to- mux to the right by drawing wires between the 2-to-4 decode and the AND gates I I I 2 I 3 = = AND Gates acting as barrier gates = = Final OR gate takes 3 zero s and one selected input 2-to-4 Decoder
19 8.9 Building a Mux To build a mux Decode the select bits and include the corresponding data input. Finally OR all the first level outputs together. I i i i2 = 2 I I 2 I I I i3 I 3
20 8.2 Building a Mux To build a mux Decode the select bits and include the corresponding data input. Finally OR all the first level outputs together. = 2 I I I 2 I 3 i i i2 i3 I 3 I 3 I 3
21 OEL OEL OEL2 OEL3 8.2 Recall Using T/T2 st Level of AND gates act as barriers only passing channel OR gates combines 3 streams of s with the channel that got passed (i.e. ICH) 2 nd Level of AND gates passes the channel to only the selected output Essentially this logic forms a 4-to- mux where one level of gates blocks all but and then the OR gate combines all signals ICH ICH ICH Connection Point ICH ICH ICH OCH OCH ICH 2 ICH OCH 2 ICH 3 ICH ICH OCH 3 IEL IEL IEL2 IEL3 2-to-4 Decoder AND: AND ICH = ICH AND ICH =
22 to- Multiplexers 2-to- Mux A i 2 Thus, input = B is selected and passed to the output B y i s elect bits = 2 =. B i I
23 8.23 Building a 2-to- Mux To build a mux Decode the select bits and include the corresponding data input. Finally OR all the first level outputs together. I I
24 8.24 Building Large Muxes imilar to a tournament of sports teams Many teams enter and then are narrowed down to winner In each round winners play winners tage 3 Final output tage 2 tage Railroad witch tation
25 Design an 8-to- mux with 2-to Muxes I I I I I I2 I3 I I I I I4 I I5 I I 2 I I6 I7 I I I 2
26 8.26 Cascading Muxes Use several small muxes to build large ones Rules. Arrange the muxes in stages (based on necessary number of inputs in st stage) 2. Outputs of one stage feed to inputs of the next until only final output 3. All muxes in a stage connect to the same group of select bits Usually, LB connects to first stage MB connect to last stage
27 8.27 Building a 4-to- Mux tage tage 2 D I Rule : Outputs from stage connect to inputs of stage 2 D I I I D 2 I D 3 I 4-to- mux built w/ 2-to- muxes Rule 2: LB connect to all muxes in first stage. MB connects to all muxes in second stage
28 8.28 Building a 4-to- Mux tage tage 2 D I D D D I I D 2 D 3 D 2 I I Walk through an example: D 3 I =
29 8.29 Building a 4-to- Mux tage tage 2 D I D D D 2 D I D I D 3 D 2 I D 3 I Walk through an example: = D 3 I = narrows our choices down to D and D 3
30 8.3 Building a 4-to- Mux tage tage 2 D I D D D I D I D 2 D D 3 D 2 I D 3 I Walk through an example: = D 3 I = selects our final choice, D
31 8.3 Device vs. ystem Labels When using hierarchy (i.e. building blocks) to design a circuit be sure to show both device and system labels Device Labels: ignal names used inside the block Placeholder names the designer of the block uses to indicate which input/output is which to the outside user (Names may vary; read the manual) ystem labels: ignal names used outside the block Actual signals from the circuit being built Can have the same name as the device label if such a signal name exists at the outside level Analogy: Formal and Actual parameters in software function calls. a and b are like device labels and indicate the names used inside a block. 2. x and y are like system labels and represent the actual values to be used. int div(int i, int i) { int t = i/i; return t; } int main() { int d=, d=2; int s = div(d,d); } Device Labels: Indicate which input/output is which inside the bock. ystem Labels: Actual signals from the circuit being built D D D 2 D 3 I I I I I I
32 8.32 Exercise ketch how you could build a 6-to- mux with 4-to- muxes? 8-to- and 2-to muxes?
33 8.33 Exercise Create a 3-to- mux using 2-to- muxes Inputs: I, I, I2 and select bits, Output: I I D D I I D 2 I2 I I
34 8.34 elect-bit Ordering If we connect the select bits as shown to build an 8-to- mux, show how to label the inputs (i-i7) so that the correct input is passed based on the binary value of 2: 8 elects OUT 2 i i4 i2 i6 i i5 i3 i7 2
35 8.35 Another way to multiplex TRI-TATE GATE
36 8.36 Gates can output two values: & Typical Logic Gate Logic (Vdd = 3V or 5V), or Logic (Vss = GND) But they are ALWA outputting something!!! Analogy: a sink faucet 2 possibilities: Hot ( ) or Cold ( ) In a real circuit, inputs cause EITHER a pathway from output to VDD OR V +3V +3V Hot Water = Logic Cold Water = Logic (trapped together so always one type of water coming out) Inputs Transistors to allow high voltage to pass Transistors to allow low voltage to pass Output Inputs Transistors to allow high voltage to pass Transistors to allow low voltage to pass Output Vdd Vss Inputs
37 8.37 Output Connections Can we connect the output of two logic gates together? No! Possible short circuit (static, low-resistance pathway from Vdd to GND) We call this situation bus contention rc Vdd Inputs rc Vss Vdd Inputs rc 2 rc 2 Vss
38 8.38 Tri-tate Buffers Normal digital gates can output two values: &. Logic = volts 2. Logic = 5 volts Tristate buffers can output a third value: 3. Z = High-Impedance = "Floating" (no connection to any voltage source infinite resistance) Analogy: a sink faucet 3 possibilities:.) Hot water, 2.) Cold water, 3.) NO water Inputs Hot Water = Logic Cold Water = Logic NO Water = Z (High-Impedance) +3V Transistors to allow high voltage to pass Z (high impedance) Transistors to allow low voltage to pass Output
39 8.39 Tri-tate Buffers Tri-state buffers have an extra enable input When disabled, output is said to be at high impedance (a.k.a. Z) High Impedance is equivalent to no connection (i.e. floating output) or an infinite resistance It's like a brick wall between the output and any connection to source When enabled, normal buffer Tri-tate Buffer In Out = In E Enable= In Out = E Enable= En In Out - Z
40 8.4 Tri-tate Buffers We use tri-state buffers to share one output amongst several sources Rule: Only buffer enabled at a time rc E EN rc 2 EN2 E D D-FF CLK Q Q rc 3 E EN3
41 8.4 Tri-tate Buffers We use tri-state buffers to share one output amongst several sources Rule: Only buffer enabled at a time When buffer enabled, its output overpowers the Z s (no connection) from the other gates elect source to pass its data E output of overpowers the Z E Z D D-FF CLK Q Q E Z Disabled buffers output Z
42 8.42 Enable Polarity ide note: ome tri-states are design to pass the input (be enabled) when the enable is (rather than ) A inversion bubble is shown at the enable input to indicate the "low" polarity needed to enable the tristate In E Out = In In E Out = In Enable= Enable= In E Out = Z In E Out = Z Enable= Enable= En In Out - Z En In Out - Z
43 8.43 Communication Connections Multiple entities need to communicate We could use Point-to-point connections A shared bus (set of wires) eparate point to point connections hared Bus
44 8.44 Bidirectional Bus transmitter (otherwise bus contention) N receivers Each device can send (though at a time) or receive
45 8.45 Tri-tate Gates Advantage: don t have to know in advance how many devices will be connected together Tri-tate gates give us the option of connecting together the outputs of many devices without requiring a circuit to multiplex many signals into one Just have to make sure only one is enabled (output active) at any one time. src src2 src3 MUX ource w/ Tri-tate Gates src src2 src3 ingle output srcn Input elect Output Enables srcn
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