ELEC451 Integrated Circuit Engineering Fall 2009 Solution to CAD Assignment 2 Inverter Voltage Transfer Characteristic (VTC)

Transcription

1 ELEC451 Integrated Circuit Engineering Fall 2009 Solution to CAD Assignment 2 Inverter Voltage Transfer Characteristic (VTC) The plot below shows how the inverter's threshold voltage changes with the relative strength of the NMOS and PMOS transistors. The larger the PMOS transistor gets, the higher the inverter threshold voltage is (chip makers use this effect to provide specialty logic families with non-standard input thresholds, like TTL-compatible input levels for their "HCT" logic family). From the plots we can also estimate the threshold voltages V T of the two transistors: when V IN puts us "below" the threshold voltage of each transistor, it is OFF, and the VTC curve hits VDD (marker M1 for NMOS off) or 0 volts (marker M2 for PMOS off).

2 Inverter Transient Behaviour The inv1 cell with minimum sized transistors for both NMOS and PMOS will have different values for t PHL and t PLH values because the PMOS is much weaker (less current flow for the same voltage drops). I got a rising initial slope of (290 mv/60 ps) = 4.8 V/nsec (saturated PMOS charging C L = 20 ff), and a falling initial slope of (287 mv/22 ps) = 13.2 V/nsec (saturated NMOS discharging C L = 20fF). The slope of a capacitor's voltage equals its current divided by its capacitance, so I estimate the PMOS and NMOS saturation currents as: I p DSAT = C L dv/dt = (20fF) * (4.8 V/nsec) = 96 ua I n DSAT = C L dv/dt = (20 ff) * (13.2 V/nsec) = 264 ua These computed values agree pretty well with the currents at the far right edge of the I SD and I DS plots from CAD Assignment #1. Note that fro this computation I have ignored the contribution of internal transistor parasitic capacitances, since they are very much smaller than the 20fF external load C L. The plot below shows the effect of changing capacitive load C L. Note that the t PHL and t PLH delays are not in excat proportion to load CL alone because there is added delay due to internal transistor parasitic capacitance the delays are in fact proportional to total capacitance (which we will consider soon in the course).

3 The plot below shows delays for invwp_tran schematic (with an increased 50 ff load now) after the PMOS width has been changed to 1.26 microns (triple the NMOS width). At this value, t PHL and t PLH are fairly close at about 170 psec (the plot below was not required for hand-in). You could also have tried running this at the lower 20 ff load by editing the value of the "C0" component on the schematic, and you would see smaller absolute delays, but again both rising and falling delays would be well matched.

4 Transmission Gate and Pass-logic Behaviour Transmission gate delays are shown below. I measured a t PLH of 202 psec, and a t PHL of 145 psec. If you recall that in our modeling the rising propagation delay is approximately determined by R p 2R n, and the falling delay by R n 2R p, the ratio of the measured t PLH and t PHL is just about right (if you plug in R p = 3R n ). For the plot below, only a single NMOS-only pass gate is used. Note how the high logic level is degraded from 1.8V down to 1.1 volts, a loss of 0.68V. This is higher than the expected V n T= 0.42 volts estimated earlier, and is due to something called the "body effect'' ( when the source terminal is not at the same voltage as the NMOS's substrate, the threshold voltage actually increases). Also note how the output voltage only creeps slowly toward its final (degraded) high level, as the NMOS is becoming almost fully OFF.

5 Cascaded Logic: Slope Behaviour NO hand-in was required for this part. The plot below shows the signals through the inverter cascade. The average of t PHL and t PLH through the first inverter is t P = ( )/2 = 224 psec. Through the second inverter, I get an average t P of ( )/2 = 328 psec - the increased delays are due to slope effect (the sloped output of inverter 1 is driving inverter 2, whereas inverter 1 was driven with a signal with a slope time of t slope =0). Through the third inverter, I get an average t P of ( )/2 = 326 psec. Note that the third inverter's delays are no bigger - it actually benefitted slightly from an opposite polarity signal with slopes better matched to its transistors than was the case in inverter 2.