ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Fall Notes - Unit 3

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1 EECTRIC ND COMPUTER ENGINEERING DEPRTMENT, OKND UNIVERITY ECE-7: Digital ogic Design all 7 IMPEMENTTION TECNOOGY Notes - Unit 3 OGIC EVE: ogic values are represented by TRUE or E. In digital circuits, it is customary to represent them using voltage values: igh voltage values are represented by (or TRUE), and ow voltage values are represented by (or E). The value of depends on the I/O standard. or example: TT (5v), VTT (3.3v), VCMO (.5), VCMO (.). Undefined s for the symbols and, there are two ways to assign them: Positive ogic: The symbol is assigned to. The symbol is assigned the. Negative ogic: The symbol is assigned to. The symbol is assigned the. Example: logic circuit has the following truth table. Using positive logic, the circuit represents an ND gate. Using negative logic, the circuit represents an OR gate. mall triangles are included in the gate s terminals to indicate we are using negative logic. TRUT TE O GTE Positive ogic Input and output interface pins can either be activated by a ow () or a igh () value. ere, the distinction between positive and negative logic is important. Negative ogic ctive ow witch ctive ow ED ctive igh witch Example: We want a circuit that activates an ED when the inputs are activated. ut the inputs (switches) and output (ED) are active low. ere, negative logic seems better suited to represent this logic circuit: we need an ND gate in negative logic. TRUT TE O GTE Negative ogic What about implementation? We use gates in positive logic: to do that, we replace the triangles with inverters, and finally what we need is just an OR gate. TRUT TE O GTE Positive ogic In conclusion, when encountering an active low input or output, include an inverter, and then just use positive logic. It is common to have a variety of input/output pins, some being active low and others being active high. ctive igh ED Instructor: Daniel lamocca

2 EECTRIC ND COMPUTER ENGINEERING DEPRTMENT, OKND UNIVERITY ECE-7: Digital ogic Design all 7 CMO OGIC GTE: CMO (Complementary MO): This type of gates includes PMO and NMO transistors. Example: NOT gate, NND gate, NOR gate. T T T Y T T T 3 T 4 Y T 3 T T 4 T T T T T 3 T 4 T T T 3 T 4 on off off on on on off off on off off on off on on off off off on on on on off off on off off on off on on off off off on on NOT gate NND gate NOR gate We can implement a logic function using just transistors. This is more efficient resource-wise. owever, for large designs, using logic gates is a better systematic way. TRI-TTE UER: uffers: They can drive more current (e.g.: motors, high-power EDs) than simple logic gates. common implementation uses OPMPs. = =' Tri-state uffers: = = Z = = = = Z = = Z tate: This is high impedance, which effectively means that is disconnected from. pplications: Multiplexors, idirectional pins, Microprocessor uses. Example: i-directional port (4 bits): IN_DT OUT_DT 4 4 DT DT IN_DT OUT_DT Instructor: Daniel lamocca

3 EECTRIC ND COMPUTER ENGINEERING DEPRTMENT, OKND UNIVERITY ECE-7: Digital ogic Design all 7 TRNMIION GTE This simple circuit behaves like a tri-state buffer. owever, a tri-state buffer requires a NOT gate, and a buffer to drive high currents. Tri-state uffer pplications: MUs, OR gate. Z PRCTIC PECT Digital circuits are analog circuits! PROPGTION DEY: t P: Propagation delay. t P t P NOIE MRGIN Voltage definitions: The input voltages V I, V I are supposed to be generated by the output of other gates. V O: Voltage produced by a gate when the output is IG. V O: Voltage produced by a gate when the output is OW. V I: Maximum input voltage that the gate will interpret as OW. V I: Minimum input voltage that the gate will interpret as IG. In the figure below, we are using positive logic by assigning the logic value to the high level value (), and the logic value to the low level value (). Noise margin: bility of the gate to tolerate noise. Electronic circuits are constantly subjected to random perturbation, called noise, which can alter the output voltage levels produced by a gate. This noise should not cause the receiving gate to misinterpret a low level value as a high one, a high as a low, or enter into a forbidden state. ow noise margin: NM = V I V O igh noise margin: NM = V O V I VO V I V I V O Generated as output of a gate '' '' V O V I V I V O Valid '' '' Noise Margin orbidden '' Noise Margin Valid '' '' '' Received on an input of a gate 3 Instructor: Daniel lamocca

4 EECTRIC ND COMPUTER ENGINEERING DEPRTMENT, OKND UNIVERITY ECE-7: Digital ogic Design all 7 ZRD digital circuit can generate glitches, which are fast spikes, usually unwanted. Glitches caused by the propagation delays and/or the structure of the circuit are known as hazards. Two types of hazard exist: tatic azards: They occur when the propagation delays are unbalanced. It can be addressed by adding all prime implicants to a function. These hazards happen when inputs change, but the output is not supposed to change. Two types:, or. Example: ll gates have a propagation delay of 5 ns. a 5 ns a b p f b c nb c nb q p q f Dynamic hazards: They are caused by the structure of the circuit. They are difficult to detect and address. They usually occur in multilevel circuits. To avoid, use only two-level circuits and ensure that there are not static hazards. Two types:, or. ignificance of hazards: synchronous circuits: They are very vulnerable to hazards and will usually render the circuits unusable. ynchronous circuits: azards do not pose a problem here, as we use registers to safely ignore hazards. Combinational circuits: azards are usually not a problem because the outputs solely depend on the current inputs (as long as the duration between input changes is greater than the propagation delay, which is usually the case). PROGRMME OGIC DEVICE TT (Transistor-Transistor logic) chips were commonly used to implement logic functions. Each one contains a few logic gates. The function of a TT chip is fixed and cannot be modified to suit a particular design requirement. TT chips are becoming obsolete for new designs. Programmable ogic Devices (PDs) contain relatively large amounts of logic gates with a structure that is not fixed. PD is a general-purpose chip for implementing logic circuitry. PD contains logic gates and programmable switches. Once programmed, PDs maintain the configured circuitry, i.e., PDs are non-volatile. PDs are further classified into imple PDs (PDs) and Complex (CPDs). They are suitable for relatively small to medium applications. good overview is presented in: PG and CPD architectures: Tutorial,. rown, J. Rose, IEEE Design & Test of Computers, vol. 3, no., ummer 996, pp IMPE PD (PD): Programmable ogic rray (P): It contains input buffers and inverters, an ND plane, and an OR plane. The ND and OR planes are configurable. Programmable rray ogic (P): imilar to a P, but the OR plane is fixed. This is simpler to manufacture, but offers less flexibility. Output pins of a P/P: In order to support sequential circuits (synchronous, asynchronous), extra circuitry is added to the output pins. This extra circuitry commonly includes a flip flop, a multiplexor, a tri-state buffer and wires to feedback the output back to the ND plane. The extra circuitry along with the OR gates is called macrocell. COMPE PD (CPD) They include multiple P-like blocks, with internal wiring resources to connect the circuit blocks. Each P-like block is also connected to subcircuit labeled I/O block. Commercial CPDs range in size from to P-like blocks. Commercial CPDs have an equivalent of up to, logic gates, which is not too large. Example of commercial CPDs: ltera M7, ilinx Coolrunner-II. 4 Instructor: Daniel lamocca

5 EECTRIC ND COMPUTER ENGINEERING DEPRTMENT, OKND UNIVERITY ECE-7: Digital ogic Design all 7 IED PROGRMME GTE RRY (PG) PGs have large logic capacity and support the implementation of large logic circuits. They are volatile, so they have to be continuously power to maintain their configuration. They do not contain ND or OR planes. Instead, logic blocks are used to implement the required function. Three main types of resources: logic blocks, I/O blocks, and interconnection wires and switches. Example of commercial PGs: ilinx Virtex-4/5/6, 7-series: Virtex-7, rtix-7, Kintex-7. CONIGURE OGIC OCK (C): It contains UTs (ook-up Tables) that implement the logic function. UT is also called a function generator, and it contains storage cells that can be programmed by a or. -input UT: This circuit, depicted below, is equivalent to a 4-to- MU with inputs being the contents of the memory cells. The contents of the storage cells are the minterms of the function f(, ). y modifying the contents of the memory cells, we can produce any -variable oolean function. -to- ook-up Table UT to address (Read-only memory with 4 positions) data() data() data() data(3) data() data() data() data(3) memory cells 3 3 The table below shows 3 functions that were generated by selecting particular values for the contents of the memory cells. Minterms 3 data() = m = data() = m = data() = m = 3 data(3) = m 3 = n-input UT: We can build larger UTs by using more MUs. n n-input UT can implement any n-variable oolean function. Commercial devices usually implement UTs of 4 to 6 inputs. ilinx Virtex-/Virtex-4: 4-input UTs ilinx Virtex-6/7-series: 6-input UTs Each UT is connected to a flip flop and a multiplexer. PROGRMMING PD, PG In a PD, the connection between logic signals and the gates in the ND/OR planes are specified by programmable switches. In an PG, the programmable switches allow the logic blocks to be interconnected. Commercial PDs have a few thousand switches, and PG can have millions. ence, it is not feasible for a user to specify manually the desired programmed state of each switch. Instead, CD systems are employed: once the user completes the design of a circuit, the CD tools generate a file, often called a programming file or fuse map, that specifies the state of each switch in the PD for a given circuit. or an PG, the file is usually called the bistream file. PDs/PGs have a dedicated programming unit, to which the programming file is streamed to. Programmable witches: Old technology: metal-alloys fuses were used as programmable links. Each pair of horizontal and vertical wires that cross is connected by a small metal fuse. To program, the fuse is melted for every connection that is not wanted on the circuit. The process is non-reversible. In current PDs, CPDs, programmable switches are implemented by programmable transistors: Erasable PROM (EPROM) transistor Electrically erasable PROM (EEPROM) transistor In current PGs, the programming information is stored in memory cells, called static random access memory (RM) cells. RM cells are used to store data (truth table values) of the UTs as well as the configuration of the interconnection wires on an PG. The collection of RM cells is called Configuration Memory. Due to the use RM technology, data is lost when the memory is not powered. Thus, the PG configuration is volatile. 5 Instructor: Daniel lamocca