! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential MOS Logic Classes of Logic Circuits two stable op pts Latch level triggered Flip-Flop edge triggered one stable op pt One-shot single pulse output no stable op pt Ring Oscillator Combinational Circuits: a Current Output(s) depend ONLY on Current Inputs b Suited to problems that can be solved using truth tables Sequential Circuits or State Machines: a Current Output(s) depend on Current Inputs and Past Inputs via State(s) b Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner 6 Sequential Circuit (or State Machine) Construct Synchronous Discipline Inputs Outputs V o1 Vo2 V o3! Add state elements (registers, latches)! Compute " From state elements " Through combinational logic " To new values for state elements Present State REGISTER Clock -> Register is used to Store Past Values of State(s) and Output(s) -> Synchronous Sequential Circuit clock, outputs change with clock event -> Asynchronous Sequential Circuit no clock, outputs change after inputs change Next State 7 8 1

2 Static Bistable Sequential Circuits Static Bistable Sequential Circuits Basic Crosscoupled Inverter Basic Crosscoupled Inverter 9 10 Static Bistable Sequential Circuits Basic Crosscoupled Inverter Static Bistable Sequential Circuits Basic Crosscoupled Inverter V OH = V DD V OL = 0 maintain stable state STATIC: V DD and GND are required to maintain a stable state Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State Basic Sequential Circuits (Cells)! Latches! Registers Latch! Level-sensitive device! Positive Latch " Output follows input if CLK high! Negative Latch " Output follows input if CLK low = CLK + CLK In

3 Register Shift Register! Edge-triggered storage element! How do you make a shift register out of latches?! Positive edge-triggered " Input sampled on rising CLK edge! Negative edgetriggered " Input sampled on falling CLK edge 15 Penn ESE 570 Spring Khanna 16 Positive-Edge Triggered Register Positive-Edge Triggered Register! Build register from of latches! What happens when φ 0 is high?! What happens when φ 1 is high?! Build register from of latches M M Positive-Edge Triggered Register Positive-Edge Triggered Register! Build register from of latches! Build register from of latches! What could go wrong if clocks overlap?! Control with non-overlapping clocks M

4 Two Phase Non-Overlapping Clocks Latch Timing Issues! What timing constraints do we have?! What timing constraints do latches impose? " When can φ change? " How long must φ be high? " Delay when φ is high? Penn ESE 570 Spring Khanna 21 Penn ESE 570 Spring Khanna 22 Clocking Discipline Timing Hazards! Follow discipline of combinational logic broken by registers! Compute " From state elements " Through combinational logic " To new values for state elements! As long as clock cycle long enough, " Will get correct behavior 23 Penn ESE 570 Spring Khanna 24 Latch Timing Issues Latch Timing Issues! t su =time data (D) must be valid before CLK edge! t plogic =worst case propogation delay of logic! t c-p =worst case propogation delay of latch Penn ESE 570 Spring Khanna 25 Penn ESE 570 Spring Khanna 26 4

5 Latch Timing Issues! t cdregister =minimum propogation delay of latch! t cdlogic =minimum propogation delay of logic! t hold =time data (D) must stay valid after CLK edge * * Penn ESE 570 Spring Khanna basic crosscoupled inverter basic crosscoupled inverter HOLD OP: S = 0, R = 0 HOLD OP: S = 0, R = 0 basic crosscoupled inverter basic crosscoupled inverter

6 SET OP: S = 1, R = 0 RESET OP: R = 1, S = 0 basic crosscoupled inverter basic crosscoupled inverter CMOS SR Latch NAND2 ACTIVE HIGH ACTIVE LOW * * * * * * CMOS SR Latch NAND2 Synchronous Latches NAND SR SR Latch LATCH NOTE: S and R are asynchronous basic cross-coupled inverter S/R CK S /R'

7 Latch Static CMOS TG D-LATCH! Level-sensitive device! Positive Latch " Output follows input if CLK high! Negative Latch " Output follows input if CLK low = CLK + CLK In D CK CK CK CK Static CMOS TG D-LATCH 8 Transistors Static CMOS TG D-LATCH 8 Transistors When CK = 1 output = D, and tracks D until CK = 0, the D-Latch is referred to positive level triggered When CK 1 to 0, the = D is captured, held (or stored) in the Latch D-LATCH Timing Requirements CMOS D Edge Triggered Flip-Flop Negative D-Latch NMOS PMOS Positive D-Latch 43 Positive Edge Triggered D Flip-Flop = Negative D-Latch + Positive D-Latch Negative Edge Triggered D Flip-Flop = Positive D-Latch + Negative D-Latch 44 7

8 Impact of Non-ideal Clock on D-Latch Operation Two-Phase Clocked D-Latch (non-overlapping) CLK ideal CLK non-ideal ϕ 1 ϕ 1 CLK t CLK + τ D t t ϕ 2 ϕ 2 NMOS PMOS t ϕ 1 NMOS PMOS ϕ 1 ϕ 2 CLK & CLK CLK & CLK + τ D 45 ϕ 2 46 Non-overlapping Clocks Sequential Logic Timing Considerations! Play with in Cadence " Will need for project Penn ESE 570 Spring Khanna 47 Penn ESE 570 Spring Khanna 48 Timing Metrics System Timing Constraints Penn ESE 570 Spring Khanna 49 Penn ESE 570 Spring Khanna 50 8

9 Bistable Elements! The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states)! Have to be able to change the stored! Two approaches used " cutting the feedback loop (mux based latch) " overpowering the feedback loop (as used in SRAMs) Mux Based Latches! Change the stored value by cutting the feedback loop Penn ESE 570 Spring Khanna 51 Penn ESE 570 Spring Khanna 52 Tx Gate Implementation of Mux PassT Implementation of Mux Penn ESE 570 Spring Khanna 53 Penn ESE 570 Spring Khanna 54 Controller/Controlled ET Flip Flop Controller/Controlled Implementation Controller Controlled Controller Controlled Penn ESE 570 Spring Khanna 55 Penn ESE 570 Spring Khanna 56 9

10 Controller/Controlled Implementation Timing Properties Controller Controller transparent Controlled hold Controlled Controller hold Controlled transparent! Assume propagation delays are t pd_inv and t pd_tx, and that the inverter delay to derive!clk is 0! Set-up time - time before rising edge of clk that D must be valid " t su = 3 * t pd_inv + t pd_tx! Propagation delay - time for M to reach " t c-q = t pd_inv + t pd_tx! Hold time - time D must be stable after rising edge of clk " t hold = zero Penn ESE 570 Spring Khanna 57 Penn ESE 570 Spring Khanna 58 Setup Time Simulation Setup Time Simulation Penn ESE 570 Spring Khanna 59 Penn ESE 570 Spring Khanna 60 System Timing Constraints Dynamic Logic Penn ESE 570 Spring Khanna

11 Logic Comparison Overview Logic Comparison Overview word bit N2 P1 P2 A A_b N1 N3 bit_b N4 DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances Outputs are generated in response to input voltage levels and a clock Requires periodic updating or refresh WL CBL BL M1 C S DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances Outputs are generated in response to input voltage levels and a clock Requires periodic updating or refresh Comparison of Logic Implementations Comparison of Logic Implementations Y Y Ratioed Ratioed Comparison of Logic Implementations Comparison of Logic Implementations Y Y Ratioed Ratioed V DD 1 more robust

12 Dynamic CMOS Precharge Dynamic CMOS Precharge V DD Z CK A M p M e Z Z of C is complete Dynamic (Clocked) Logic: Example Comparison of Static and Dynamic Logic ADVANTAGES? DISADVANTAGES? CK = 0 => Z =? CK = 1 => Z =? Comparison of Static and Dynamic Logic Comparison of Static and Dynamic Logic

13 Cascaded Dynamic Logic Cascaded Dynamic Logic Cascaded Dynamic Logic Cascaded Dynamic Logic Domino Logic Requirements! Single transition " Once transitioned, it is done # like domino falling! All inputs at 0 during precharge " Outputs pre-charged to 1 then inverted to 0 " Ie Inputs are pre-charge to 0! Non-inverting gates

14 Cascaded Domino CMOS Logic Gates Cascaded Domino CMOS Logic Gates propagating Cascaded Domino CMOS Logic Gates Ideas propagating! Synchronize circuits " to external events (eg Clk) " disciplined reuse of circuitry! Leads to clocked circuit discipline " Uses state holding element (eg Latches and registers) " Prevents " Timing assumptions " (More) complex reasoning about all possible timings! Dynamic/clocked logic " Only build/drive one pulldown network " Fast transition propagation " Domino Logic allows for cascading Admin! HW 7 due 4/5 " Only choose the multiplier if you have designed an adder before " but you don t have to 85 14

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