Combinational Logic Design CH002
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1 Combinational Logic Design CH002
2 Figure 2.1 Circuit as a black box with inputs, outputs, and specifications
3 Figure 2.2 Elements and nodes
4 Figure 2.3 Combinational logic circuit
5 Figure 2.4 Two OR implementations
6 Figure 2.5 Multiple-output combinational circuit
7 Figure 2.6 Slash notation for multiple signals
8 Figure 2.7 Example circuits
9 Figure 2.8 Truth table and minterms
10 Figure 2.9 Truth table with multiple TRUE minterms
11 Figure 2.10 Ben's truth table
12 Figure 2.11 Ben's circuit
13 Figure 2.12 Random three-input truth table
14 Figure 2.13 Truth table with multiple FALSE maxterms
15 Figure 2.14 Identity theorem in hardware: (a) T1, (b) T1
16 Figure 2.15 Null element theorem in hardware: (a) T2, (b) T2
17 Figure 2.16 Idempotency theorem in hardware: (a) T3, (b) T3
18 Figure 2.17 Involution theorem in hardware: T4
19 Figure 2.18 Complement theorem in hardware: (a) T5, (b) T5
20 Figure 2.19 De Morgan equivalent gates
21 Figure 2.20 Truth table showing
22 Figure 2.21 Truth table showing minterms for
23 Figure 2.22 Truth table proving T11
24 Figure 2.23 Schematic of
25 Figure 2.24 Wire connections
26 Figure 2.25 Schematic of
27 Figure 2.26 Schematic using fewer gates
28 Figure 2.27 Priority circuit
29 Figure 2.28 Priority circuit schematic
30 Figure 2.29 Priority circuit truth table with don't cares (X's)
31 Figure 2.30 Three-input XOR: (a) functional specification and (b) two-level logic implementation
32 Figure 2.31 Three-input XOR using two-input XORs
33 Figure 2.32 Eight-input XOR using seven two-input XORs
34 Figure 2.33 Multilevel circuit using NANDs and NORs
35 Figure 2.34 Bubble-pushed circuit
36 Figure 2.35 Logically equivalent bubble-pushed circuit
37 Figure 2.36 Circuit using ANDs and ORs
38 Figure 2.37 Poor circuit using NANDs and NORs
39 Figure 2.38 Better circuit using NANDs and NORs
40 Figure 2.39 Circuit with contention
41 Figure 2.40 Tristate buffer
42 Figure 2.41 Tristate buffer with active low enable
43 Figure 2.42 Tristate bus connecting multiple chips
44 Figure 2.43 Three-input function: (a) truth table, (b) K-map, (c) K-map showing minterms
45 Figure 2.44 K-map minimization
46 Figure 2.45 K-map for Example 2.9
47 Figure 2.46 Solution for Example 2.9
48 Figure 2.47 Seven-segment display decoder icon
49 Figure 2.48 Seven-segment display digits
50 Figure 2.49 Karnaugh maps for S a and S b
51 Figure 2.50 K-map solution for Example 2.10
52 Figure 2.51 Alternative K-map for S a showing different set of prime implicants
53 Figure 2.52 Alternative K-map for S a showing incorrect nonprime implicant
54 Figure 2.53 K-map solution with don't cares
55 Figure :1 multiplexer symbol and truth table
56 Figure :1 multiplexer implementation using two-level logic
57 Figure 2.56 Multiplexer using tristate buffers
58 Figure :1 multiplexer
59 Figure :1 multiplexer implementations: (a) two-level logic, (b) tristates, (c) hierarchical
60 Figure :1 multiplexer implementation of two-input AND function
61 Figure 2.60 Multiplexer logic using variable inputs
62 Figure 2.61 Alyssa's circuit: (a) truth table, (b) 8:1 multiplexer implementation
63 Figure 2.62 Alyssa's new circuit
64 Figure :4 decoder
65 Figure :4 decoder implementation
66 Figure 2.65 Logic function using decoder
67 Figure 2.66 Circuit delay
68 Figure 2.67 Propagation and contamination delay
69 Figure 2.68 Short path and critical path
70 Figure 2.69 Critical and short path waveforms
71 Figure 2.70 Ben's circuit
72 Figure 2.71 Ben's critical path
73 Figure 2.72 Ben's shortest path
74 Figure :1 multiplexer propagation delays: (a) two-level logic, (b) tristate
75 Figure :1 multiplexer propagation delays: hierarchical using 2:1 multiplexers
76 Figure 2.75 Circuit with a glitch
77 Figure 2.76 Timing of a glitch
78 Figure 2.77 Input change crosses implicant boundary
79 Figure 2.78 K-map without glitch
80 Figure 2.79 Circuit without glitch
81 Figure 2.80 Truth tables for Exercises 2.1 and 2.3
82 Figure 2.81 Truth tables for Exercises 2.2 and 2.4
83 Figure 2.82 Circuit schematic
84 Figure 2.83 Circuit schematic
85 Figure 2.84 Circuit schematic
86 Figure 2.85 Truth table for Exercise 2.28
87 Figure 2.86 Truth table for Exercise 2.31
88 Figure 2.87 Multiplexer circuit
89 Figure 2.88 Multiplexer circuit
90
91
92 Figure u02-01
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