EE141-Spring 2007 Digital Integrated Circuits
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1 EE141-Spring 2007 Digital Integrated Circuits Lecture 22 I/O, Power Distribution dders 1 nnouncements Homework 9 has been posted Due Tu. pr. 24, 5pm Project Phase 4 (Final) Report due Mo. pr. 30, noon Poster presentations Tu. May 1 st, 3-6pm Final Exam Mo. May 14, 5-8pm, 145 McCone 2
2 Class Material Last lecture Timing Clock distribution Today s lecture I/O Power distribution Intro to adders Reading Chapter 11 3 Impact of Interconnect Design Issues 4
3 V ( V o l t ) Impact of Capacitance Capacitive Crosstalk-Dynamic Node V Y CXY = C + C Y XY V X CLK C XY Y In 1 In 2 In 3 PDN C Y X 2.5 V CLK 0 V 3 x 1 µm overlap: 0.19 V disturbance 5 Capacitive Cross Talk Driven Node V X R Y C XY C Y X Y t r τ XY = R Y (C XY +C Y ) t (nsec) 1 Keep time-constant smaller than rise time 6
4 How to attle Capacitive Crosstalk Shielding wire void large crosstalk cap s GND void floating nodes Isolate sensitive nodes V Shielding DD Control rise/fall times -> large layer Do not run wires together on GND long distances Shield! Substrate (GND) Differential signaling 7 Delay Degradation C c - Impact of neighboring signal activity on switching delay - When neighboring lines switch in opposite direction of victim line, delay increases Miller Effect - oth terminals of capacitor are switched in opposite directions (0 V dd, V dd 0) - Effective voltage is doubled and additional charge is needed (from Q=CV) - Wire length = 100 µm in 0.25 µm results in worst-case 80% t p degradation! 8
5 Driving Large Capacitances V in V out C L Transistor Sizing Cascaded uffers 9 Using Cascaded uffers In Out 1 2 N C L = 20 pf 0.25 µm process Cin =2.5fF tp0 = 30 ps F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns (See Chapter 5) 10
6 t / t 0 p p Output Driver Design Trade off Performance for rea and Energy Given t pmax find N and f rea driver Energy E driver = = N 2 N 1 f 1 F 1 ( 1+ f + f f ) min = min = min f 1 f 1 2 N 1 2 F 1 2 CL 2 ( + f + f f ) C V = C V V 1 i DD i DD DD f 1 f 1 11 Delay as a Function of F and N 10,000 F = 10, t p /t p0 100 F = 1000 F = Number of buffer stages N
7 I/O Design 13 onding Pad Design onding Pad GND 100 µm Out In GND Out 14
8 ESD Protection When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate need guard rings to pick it up. 15 Pads + ESD Protection PD R D1 X D2 C Diode 16
9 Chip Packaging L onding wire L Chip Lead frame Pin Mounting cavity ond wires (~25µm) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100µm in 0.25µm technology), with large pitch (100µm) Many chips areas are pad limited 17 Pad Frame Layout Die Photo 18
10 Chip Packaging n alternative is flipchip : Pads are distributed around the chip The soldering balls are placed on pads The chip is flipped onto the package Can have many more pads 19 Power Distribution 20
11 Impact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gates 21 RI Introduced Noise I f pre X R - V V M1 I R V 22
12 Resistance and the Power Distribution Problem efore fter Requires fast and accurate peak current prediction Heavily influenced by packaging technology Source: Cadence 23 Power Distribution Low-level distribution is in Metal 1 Power has to be strapped in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects lways use multiple contacts on straps 24
13 Power and Ground Distribution GND Logic Logic GND (a) Finger-shaped network GND (b) Network with multiple supply pins 25 3 Metal Layer pproach (EV4) 3rd coarse and thick metal layer added to the technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing Metal 3 Metal 2 Metal 1 Courtesy Compaq 26
14 4 Metal Layers pproach (EV5) 4th coarse and thick metal layer added to the technology for EV5 design Power supplied from four sides of the die Grid strapping done all in coarse metal 90% of 3rd and 4th metals used for power/clock routing Metal 4 Metal 3 Metal 2 Metal 1 Courtesy Compaq 27 6 Metal Layer pproach EV6 2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Significantly lowers resistance of grid Lowers on-chip inductance RP2/Vdd Courtesy Compaq Metal 4 Metal 3 RP1/Vss Metal 2 Metal 1 28
15 Electromigration (1) Limits dc-current to 1 m/µm 29 Electromigration (2) 30
16 Decoupling Capacitors 1 oard wiring onding wire SUPPLY C d CHIP 2 Decoupling capacitor Decoupling capacitors are added: On the board (right under the supply pins) On the chip (under the supply straps, near large buffers) 31 Decoupling Capacitors Under the die 32
17 33 dders 34
18 n Intel Microprocessor 9-1 Mux 5-1 Mux a g64 CRRYGEN node1 ck1 SUMSEL REG sum sumb to Cache 9-1 Mux 2-1 Mux b SUMGEN + LU s0 s1 LU : Logical Unit 1000um Itanium has 6 64-bit integer execution units like this one 35 it-sliced Design Control it 3 Data-In Register dder Shifter Multiplexer it 2 it 1 it 0 Data-Out Tile identical processing elements 36
19 it-sliced Datapath From register files / Cache / ypass Multiplexers Shifter dder stage 1 Loopback us Loopback us Wiring dder stage 2 Wiring Loopback us it slice 63 dder stage 3 Sum Select it slice 2 it slice 1 it slice 0 To register files / Cache 37 Itanium Integer Datapath Fetzer, Orton, ISSCC 02 38
20 Full-dder Cin Full adder Sum Cout 39 The inary dder Cin Full adder Sum Cout S = C i = C i + C i + C i + C i C o = + C i + C i 40
21 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on, Generate (G) = Propagate (P) = Delete = Can also derive expressions for S and C o based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = + 41 The Ripple-Carry dder C i,0 C o,0 C o,1 C o,2 C o,3 F F F F (= C i,1 ) S 0 S 1 S 2 S 3 Worst case delay linear with the number of bits t d = O(N) t adder = (N-1)t carry + t sum Goal: Make the fastest possible carry path circuit 42
22 Complementary Static CMOS Full dder C i C i X C i C i S C i C i C o 28 Transistors 43 Inversion Property C i F C o C i F C o S S 44
23 Minimize Critical Path by Reducing Inverting Stages Even cell Odd cell C i,0 C o,0 C o,1 C o,2 C o,3 F F F F S 0 S 1 S 2 S 3 Exploit Inversion Property 45 etter Structure: The Mirror dder "0"-Propagate C i Kill C o C i C i S "1"-Propagate Generate C i C i 24 transistors 46
24 The Mirror dder The NMOS and PMOS chains are completely symmetrical. maximum of two series transistors can be observed in the carrygeneration circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node C o. The reduction of the diffusion capacitances is particularly important. The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to C i are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. ll transistors in the sum stage can be minimal size. 47 Next Lecture dders, Multipliers 48
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