EE-382M-8 VLSI II. Early Design Planning: Back End. Mark McDermott. The University of Texas at Austin. EE 382M-8 VLSI-2 Page Foil # 1 1

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1 EE-382M-8 VLSI II Early Design Planning: Back End Mark McDermott EE 382M-8 VLSI-2 Page Foil # 1 1

2 Backend EDP Flow The project activities will include: Determining the standard cell and custom library elements needed to completely do the design with APR tools. Detailed floor-plan of the block level components. A reasonably detailed top-level floorplan using the cluster abstracts. Approximate clock routing at the top-level Approximate Power-GND routing at the top level EE 382M-8 VLSI-2 Page Foil # 2 2

3 EDP and Layout in the Design Flow Concept Technology Readiness Architecture uarchitecure EDP Front End Development Logic Circuits EDP encompasses planning from architecture to the layout. Backend Design Execution Layout Silicon Ramp Si Debug Production EE 382M-8 VLSI-2 Page Foil # 3 3

4 Standard Cell Library Effort Will be using a very minimal standard cell library for the project: ~80+ cells Basic logic gates and buffers 1 set-reset flip-flop CMOS65_SubVt.lib file was derived using a scaled 65nm.lib file Need to validate the scaled numbers with HSPICE simulations. Need to validate power spreadsheet numbers using HSPICE: S-D leakage currents Intrinsic power Need to validate area spreadsheet numbers EE 382M-8 VLSI-2 Page Foil # 4 4

5 Block Floorplanning Effort Objectives: Minimize area Determine best shape of the block Minimize total wire length Each team will do a detailed floorplan of their respective blocks. The output will be a spreadsheet analysis showing the contribution from each of the following: Power grid Clocking Signal Routing Datapath area Random logic area White space EE 382M-8 VLSI-2 Page Foil # 5 5

6 Integration Effort The integration team will be responsible for: Doing a floor plan of the top level of the chip Characterizing the top-level routing delays and determining the assertions and constraints for each cluster. They will be working with each cluster to optimize the constraints. Designing the clock routing structure: Determining the clock generation implementation (block diagrams) Determining the clock regeneration circuitry (block diagrams) Determining the reset logic. Designing the power grid. Determining the power estimation for the global clock and signal routing. Generating the power budget for each cluster. Generating the area budget for each cluster. EE 382M-8 VLSI-2 Page Foil # 6 6

7 Layout Implementation Options SPARC-T1 EE 382M-8 VLSI-2 Page Foil # 7 7

8 Layout Density & Die Size = Performance Schematic A C The layout of Block B affects the Floorplan timing of the path from A to C Higher density layout leads to smaller block sizes Layout #1 A B C Smaller block sizes lead to shorter wires Shorter wires can lead to higher frequency Layout #2 A B C Shorter wires can also lead to higher IPC by requiring fewer transmission pipe stages EE 382M-8 VLSI-2 Page Foil # 8 8

9 Layout Implementation Options Synthesis Random Logic Macro (RLM) Cell layout comes from a shared cell library Automated cell selection and placement Automated routing between cells Structured Custom (SC/SDP) Cell layout comes from a shared cell library Manual cell selection and placement Automated routing between cells Custom Design (CD) Cell layout is unique for each application Manual cell selection and placement Manual routing between cells Increasing Design Effort (And Density) EE 382M-8 VLSI-2 Page Foil # 9 9

10 Layout Implementation Options CD SC RLM ARTL Coding M M M Logic Minimization M M A Cell Placement M M A Device Sizing M A A Layout M A A CD SC RLM Timing Best Better Worst Density Best Better Worst Design Time Worst Better Best A = Automatic M = Manual RLM saves time in circuit design and layout SC saves time in layout. RLM and SDP make revisions easier. EE 382M-8 VLSI-2 Page Foil # 10 10

11 Datapath and Block Floorplanning Procedures MIPS R10K EE 382M-8 VLSI-2 Page Foil # 11 11

12 Datapath and Block Floorplanning Procedure Step 1 - Identify feedthrus for RLM or SC/DP block Step 2 - Look for opportunities for track sharing Step 3 - Define the bitpitch of the block Step 4 - Review the metal plan within the cell Step 5 - Review and plan the clock routing and placement Step 6 - Plan the critical cell placement locations Step 7 - Estimate the area of the cells and the block Step 8 - Review the power grid EE 382M-8 VLSI-2 Page Foil # 12 12

13 Feed-through or Over-the-cell (OTC) Routes Metal tracks routed over RLM, Datapath or custom block The block is neither the driver or a receiver of the signals Feedthrus use up metal tracks which impacts the internal signals of the block Carefully review datapath connectivity to account for them Sources Results Receiver Driver Bypass ALU 0 ALU 1 Feedthrus for ALU0 ALU 2 EE 382M-8 VLSI-2 Page Foil # 13 13

14 Datapath and Block Floorplanning Procedure Step 1 - Identify feedthrus Step 2 - Look for opportunities for track sharing Step 3 - Define the bitpitch of the block Step 4 - Review the metal plan within the cell Step 5 - Review and plan the clock routing and placement Step 6 - Plan the critical cell placement locations Step 7 - Estimate the area of the cells and the block Step 8 - Review the power grid EE 382M-8 VLSI-2 Page Foil # 14 14

15 Step 2: Track Sharing Minimizes the number of unique tracks in layout by opportunistically sharing tracks where possible Often allows for the smallest possible bitpitch Allows for metal layers to be more efficiently utilized Can help improve performance by shortening distances Should always be explored to improve layout efficiency and performance EE 382M-8 VLSI-2 Page Foil # 15 15

16 Step 2: Track Sharing Receiver Driver Sources Results Bypass$ First, check outside your block to see if there are any candidates for track sharing ALU 0 ALU 1 ALU 2 EE 382M-8 VLSI-2 Page Foil # 16 16

17 Step 2: Track Sharing Metal 2 Metal 4 IE_BYC_DATA<11:0> IE_RF_DATA<11:0> Next, check inside your block to see if there are any candidates for track sharing LRBL<11:0> RRBL<11:0> EE 382M-8 VLSI-2 Page Foil # 17 17

18 Step 2: Track Sharing Example EE 382M-8 VLSI-2 Page Foil # 18 18

19 Step 2: Track Sharing Example EE 382M-8 VLSI-2 Page Foil # 19 19

20 Datapath and Block Floorplanning Procedure Step 1 - Identify feedthrus Step 2 - Look for opportunities for track sharing Step 3 - Define the bitpitch of the block Step 4 - Review the metal plan within the cell Step 5 - Review and plan the clock routing and placement Step 6 - Plan the critical cell placement locations Step 7 - Estimate the area of the cells and the block Step 8 - Review the power grid EE 382M-8 VLSI-2 Page Foil # 20 20

21 Bit Pitch Defining Width of Chip AMD K5 EE 382M-8 VLSI-2 Page Foil # 21 21

22 Step 3: Define the Bitpitch Fixed cell width chosen to allow easy assembly Most often determined by metal usage within the datapath Integration efficiency would prefer one bitpitch per project Architectures lend themselves to more unique bit pitches Bitpitch A<4> A<3> A<2> A<1> A<0> Vdd Sig0 <4> Sig1 <4> Sig2 <4> Sig3 <4> Sig4 <4> Sig5 <4> Vss Vdd Sig0 <1> Sig1 <1> Sig2 <1> Sig3 <1> Sig4 <1> Sig5 <1> Vss EE 382M-8 VLSI-2 Page Foil # 22 22

23 Step 3: Define the Bitpitch Insure all blocks in a datapath stack follow the same bitpitch Bitpitch #2 Yµ Integer Register File Bypass Cache ALU 0 Arith Flags ALU 1 AGEN - LD / STA System Uops Bit Ops Shifter WB Mux Bitpitch #1 Xµ EE 382M-8 VLSI-2 Page Foil # 23 23

24 Bit Pitch Example: 3:2 Adder Bit Cell M3 & M1 Bitpitch 7.56u M4 M1 EE 382M-8 VLSI-2 Page Foil # 24 24

25 Bit Pitch Example: 4 Bit Cells stacked BIT - 4 BIT - 2 BIT - 1 Bitpitch 7.56u BIT - 0 EE 382M-8 VLSI-2 Page Foil # 25 25

26 Bit Pitch Example: Tiled Datapath EE 382M-8 VLSI-2 Page Foil # 26 26

27 Bit Pitch Example: Swizzle Don t mix and match bit pitches to avoid swizzle channels Swizzle Channel As buses get wider and the number of tracks per bit gets higher the cost of swizzle channels grows EE 382M-8 VLSI-2 Page Foil # 27 27

28 Step 3: Define the Bitpitch Wider bit pitches allow more upper level metal usage Narrower bit pitches allow shorter routes for orthogonal signals Balancing these conflicting objectives can be difficult Understand your local constraints and be aware of the tradeoffs EE 382M-8 VLSI-2 Page Foil # 28 28

29 Datapath and Block Floorplanning Procedure Step 1 - Identify feedthrus Step 2 - Look for opportunities for track sharing Step 3 - Define the bitpitch of the block Step 4 - Review the metal plan within the cell Step 5 - Review and plan the clock routing and placement Step 6 - Plan the critical cell placement locations Step 7 - Estimate the area of the cells and the block Step 8 - Review the power grid EE 382M-8 VLSI-2 Page Foil # 29 29

30 Metal Planning Metal layer, width, spacing and shielding are negotiable Negotiable means you have to plead your case to the integration leaders All of these impose a physical constraint for layout For your first attempt at convergence M1,M2 : Local routing M3,M4, M5, M6 : Data and control M7,M8 : Power, Ground, Clock, Reset, etc Assume all nets are routed in M1&M2 within your block Assume your only shielding is on clocks and reset Assume the routes are minimum EE 382M-8 VLSI-2 Page Foil # 30 30

31 Metal Flow Planning Avoid bi-directional dataflow Cntl Cntl Data Data Data BAD GOOD EE 382M-8 VLSI-2 Page Foil # 31 31

32 Shielding Intentionally routing signals to control the effective line-to-line capacitance seen during switching. Requires designers to constrain the physical assembly done by routing tools or physical design specialists (PDSs). Falls into one of three categories: Physical shielding - signals are routed next to a power rail Logical shielding - signals are routed by logically related signals Temporal shielding - signals are routed by temporally distinct signals EE 382M-8 VLSI-2 Page Foil # 32 32

33 Miller Coupling Factor A A B C B C MCF = 2.0 Both against MCF = 1.5 One against, one quiet A A A B C B C B C MCF = 1.0 Both quiet MCF = 0.5 One with, one quiet MCF = 0.0 Both with EE 382M-8 VLSI-2 Page Foil # 33 33

34 No Shielding Signals are routed next to any neighboring signals Neighbors can slow down (max delay) or speed up (min delay) signal transitions through line-to-line coupling Variation can create design problems Most signals will not be shielded No Shield Max MCF 2.0 Min MCF 0.0 A A B C B C Sig A Sig B Sig C EE 382M-8 VLSI-2 Page Foil # 34 34

35 Physical Shielding Signals are routed next to at least one power rail Helps both min delay and max delay Can be expensive in terms of metal usage Typically limited to most critical nets and clocks Half Shield Full Shield Max MCF 1.5 Min MCF 0.5 Max MCF 1.0 Min MCF 1.0 Vss Sig A Sig B Vss Sig A Vss EE 382M-8 VLSI-2 Page Foil # 35 35

36 Logical Shielding Signals are routed next to mutually exclusive neighbors Also helps min delay and max delay Comparable results as physical shielding but lesser cost Encouraged in mux structures and arrays Max MCF 1.5 Min MCF 1.0 A B Sel A Sel A Sel B Sel B Sel C Sel A Sel B Sel C C Sel C EE 382M-8 VLSI-2 Page Foil # 36 36

37 Temporal Shielding Signals are routed next to signals that limit aggressors Can help max delay or min delay or both Lesser cost than physical shielding, but more design effort Encouraged wherever possible but tricky A Max MCF 1.0 Min MCF 0.0 Ck A B B Ck C Sig A Sig B Sig C C Ck EE 382M-8 VLSI-2 Page Foil # 37 37

38 Shielding Gotcha Tools may rely on the designer to override the default coupling assumptions L A Max MCF 2.0 Min MCF 0.0 Ck Ck L B If you need temporal shielding to make your circuit meet timing, your circuit doesn t meet timing. Do not rely on it. EE 382M-8 VLSI-2 Page Foil # 38 38

39 Datapath and Block Floorplanning Procedure Step 1 - Identify feedthrus Step 2 - Look for opportunities for track sharing Step 3 - Define the bitpitch of the block Step 4 - Review the metal plan within the cell Step 5 - Review and plan the clock routing and placement Step 6 - Plan the critical cell placement locations Step 7 - Estimate the area of the cells and the block Step 8 - Review the power grid EE 382M-8 VLSI-2 Page Foil # 39 39

40 Variations of Clock Tree distribution networks Target: Metallization and Gate topology uniformity Tapered H-Tree EE 382M-8 VLSI-2 Page Foil # 40 40

41 Clock Routing Watch out for the clock, it s your most critical net Make sure the physical design treats it accordingly Help reduce clock power by eliminating unnecessary load Make sure the clock has enough via coverage Leave room for decoupling capacitors and upsizing Don t forget to account for clock routing overhead (full shield) in your metal planning EE 382M-8 VLSI-2 Page Foil # 41 41

42 Clock Routing Avoid unnecessary clock load to save active power BAD GOOD UNNECESSARY LOAD EE 382M-8 VLSI-2 Page Foil # 42 42

43 Power/Clock Grid Clock grid is interleaved between VDD and VSS on metal6 LCB Port0 Input Data Latch LCB LCB LCB Port0 Input Data Latch LCB LCB Port1 Input Data Latch LCB LCB LCB Port1 Input Data Latch LCB Bitcell Array Port0 Decoder Port1 Decoder Bitcell Array LCB Port0 Read/Write Ckt LCB LCB LCB Port0 Read/Write Ckt LCB LCB Port0 Output Latch LCB LCB LCB Port0 Output Latch LCB LCB Port1 Read/Write Ckt LCB LCB Port1 Read/Write Ckt LCB LCB Port1 Output Latch LCB LCB Port1 Output Latch LCB EE 382M-8 VLSI-2 Page Foil # 43 43

44 Clock Routing Make sure there are enough vias to get power through the clock network INSUFFICIENT VIA COVERAGE SUFFICIENT VIA COVERAGE EE 382M-8 VLSI-2 Page Foil # 44 44

45 Clock Routing Remember to count clocks as ~5-7 tracks in your wire planning! 1x 2x 1 x 1.5x 1.5x Be careful with gated clocks. Fine grain clock gating tends to drastically increase the number of unique clocks, significantly increasing the metal usage. No tools catch this before layout Vdd Clock Vss EE 382M-8 VLSI-2 Page Foil # 45 45

46 Datapath and Block Floorplanning Procedure Step 1 - Identify feedthrus Step 2 - Look for opportunities for track sharing Step 3 - Define the bitpitch of the block Step 4 - Review the metal plan within the cell Step 5 - Review and plan the clock routing and placement Step 6 - Plan the critical cell placement locations Step 7 - Estimate the area of the cells and the block Step 8 - Review the power grid EE 382M-8 VLSI-2 Page Foil # 46 46

47 Cell Placement Start with the critical path! Place cells to limit the wire load on the critical path Move less critical blocks out of the way Place clock generators to limit clock wire load Again, place most critical clock LCBs first if area is tight Ideally there should be minimal side loads Consider track sharing opportunities when placing cells Cell placement can enable or disable track sharing Optimum placement generally follows data flow EE 382M-8 VLSI-2 Page Foil # 47 47

48 Cell Placement Short critical path No side load LCB EE 382M-8 VLSI-2 Page Foil # 48 48

49 Cell Placement and Routing EE 382M-8 VLSI-2 Page Foil # 49 49

50 Datapath and Block Floorplanning Procedure Step 1 - Identify feedthrus Step 2 - Look for opportunities for track sharing Step 3 - Define the bitpitch of the block Step 4 - Review the metal plan within the cell Step 5 - Review and plan the clock routing and placement Step 6 - Plan the critical cell placement locations Step 7 - Estimate the area of the cells and the block Step 8 - Review the power grid EE 382M-8 VLSI-2 Page Foil # 50 50

51 Area Estimation All modules have an area budget in the floorplan That budget is only an educated guess Some guesses are high, and some are low You will need to enhance the quality of these estimates by more accurately estimating the area of your modules While doing this you will reduce the amount of late surprises in the design and also reduce post-layout effort by converging with accurate parasitics EE 382M-8 VLSI-2 Page Foil # 51 51

52 Area Estimation Custom cell area can be set in one of three ways Device limited layout means the device sizes set the cell area Metal limited layout means the wires set the cell area Pitch-matching means the cell area is set to match another cell Your first job is to figure out which your cell is Datapaths are metal limited in one direction (bitpitch) Arrays often are metal limited in both directions Control blocks often match a datapath or array EE 382M-8 VLSI-2 Page Foil # 52 52

53 Die Size Estimation EE 382M-8 VLSI-2 Page Foil # 53 53

54 Datapath and Block Floorplanning Procedure Step 1 - Identify feedthrus Step 2 - Look for opportunities for track sharing Step 3 - Define the bitpitch of the block Step 4 - Review the metal plan within the cell Step 5 - Review and plan the clock routing and placement Step 6 - Plan the critical cell placement locations Step 7 - Estimate the area of the cells and the block Step 8 - Review the power grid EE 382M-8 VLSI-2 Page Foil # 54 54

55 Power Grid Delivers current from the C4 bumps to the transistors Designed to deliver typical current density to the devices Increasing current density by arraying large devices can cause you to exceed the power grid s nominal design Doing this can cause performance and noise problems EE 382M-8 VLSI-2 Page Foil # 55 55

56 Power Grid Think of the grid as a straw between the C4 and the devices. Too many devices sucking through the same straw or too narrow a straw can cause devices to starve and the supply to dip or crater! EE 382M-8 VLSI-2 Page Foil # 56 56

57 SAMPLE Power/Ground GRID (Full Shielding, MCF = 1.0) λ λ 4λ 2λ 2λ 2λ 2λ 2λ VSS VDD VSS S i g Vss S i g Vss S i g S i g Vss S i g Vss S i g 48λ * Where λ is minimum critical dimension for width/space Shielding takes up significant routing resources. Global M6 routes over the array should have minimal coupling noise to array bitlines. EE 382M-8 VLSI-2 Page Foil # 57 57

58 Power Grid OUT <31:0> Bit 31 A<31:0> A <31:0> SCHEMATIC VIEW A Bit 0 RELATIVE CELL PLACEMENT CELL LAYOUT VIEW EE 382M-8 VLSI-2 Page Foil # 58 58

59 Power Grid When large, arrayed drivers pull OUT <31:0> Bit 31 A<31:0> on the same rail, supply bounce can occur degrading performance and causing supply offset noise A <31:0> SCHEMATIC Out VIEW Current Bit 0 RELATIVE CELL Vdd A PLACEMENT CELL LAYOUT Vss VIEW EE 382M-8 VLSI-2 Page Foil # 59 59

60 Power Grid Be very careful arraying large drivers Follow the % power guidelines for the power grid Try to keep temporal relationships between arrayed drivers Consider the physical impact on the grid by your design Be prepared to make the grid more robust to compensate for marginal grids EE 382M-8 VLSI-2 Page Foil # 60 60

61 Summary Early design planning and layout can have a significant impact on processor design Die size, profit & power are impacted by layout density Schedule is impacted by implementation choices Floorplanning also significantly impacts circuit performance Shielding can help timing and noise sensitive circuits Carefully floorplanning critical paths can help reduce wire loads Reducing clock routing can reduce clock skew and clock power EE 382M-8 VLSI-2 Page Foil # 61 61

62 Backup EE 382M-8 VLSI-2 Page Foil # 62 62

63 Wire and Resistance Calculator EE 382M-8 VLSI-2 Page Foil # 63 63

64 ALPHA EE 382M-8 VLSI-2 Page Foil # 64 64

65 PPC 603 EE 382M-8 VLSI-2 Page Foil # 65 65

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