EE115C Winter 2017 Digital Electronic Circuits. Lecture 11: Wires, Elmore Delay

Transcription

1 EE115C Winter 2017 Digital Electronic Circuits Lecture 11: Wires, Elmore Delay

2 The Wire transmitters receivers schematics physical EE115C Winter

3 Interconnect Impact on Chip EE115C Winter

4 Wire Models All-inclusive model Capacitance-only EE115C Winter

5 Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive EE115C Winter

6 No of nets (log scale) Nature of Interconnect Local Interconnect Pentium Pro (R) Pentium (R) II Pentium (MMX) Pentium (R) Pentium (R) III Global Interconnect S Global = S Die S Local = S Technology ,000 10, ,000 Length (mm) Source: Intel EE115C Winter

7 Outline Interconnect Capacitance Interconnect Resistance Modeling the Wire Perspective: Interconnect Issues EE115C Winter

8 Capacitance of Wire Interconnect V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L EE115C Winter

9 Capacitance: The Parallel Plate Model L Current flow W Electrical-field lines H t di Dielectric Substrate c int t di di WL S Cwire S S S L 1 S L EE115C Winter

10 Permittivity EE115C Winter

11 Fringing Capacitance (a) H W - H/2 + fringe (b) pp EE115C Winter

12 Fringing vs. Parallel Plate From: Bakoglu89 EE115C Winter

13 Interwire Capacitance fringing parallel EE115C Winter

14 Impact of Interwire Capacitance From: Bakoglu89 EE115C Winter

15 Wiring Capacitances (0.25mm Example) EE115C Winter

16 Outline Interconnect Capacitance Interconnect Resistance Modeling the Wire Perspective: Interconnect Issues EE115C Winter

17 Wire Resistance R = r L H W H L Sheet Resistance R 0 W R 1 = R 2 EE115C Winter

18 Interconnect Resistance Textbook, pg. 145 EE115C Winter

19 Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-length EE115C Winter

20 Polycide Gate MOSFET Silicide PolySilicon SiO 2 n + n + p Silicides: WSi 2, TiSi 2, PtSi 2, TaSi Conductivity: 8-10 times better than Poly EE115C Winter

21 Sheet Resistance Textbook, pg. 145 EE115C Winter

22 Modern Interconnect EE115C Winter

23 Outline Interconnect Capacitance Interconnect Resistance Modeling the Wire Perspective: Interconnect Issues EE115C Winter

24 The Lumped Model V out Driver C wire R driver V out V in C lumped EE115C Winter

25 The Distributed RC Line V rc t 2 V 2 x ( V out ) rc 2 2 L EE115C Winter

26 Step Response of RC Wire as a Function of Time and Space voltage (V) x = L / 10 x = L / 4 x = L / 2 x = L time (nsec) EE115C Winter

27 The Elmore Delay: RC Chain EE115C Winter

28 Wire Model Assume: Wire modeled by N equal-length segments For large values of N: EE115C Winter

29 The Lumped RC Model The Elmore Delay Di N k 1 C k R ik EE115C Winter

30 RC Models (The Way Spectre Does It ) EE115C Winter

31 Driving an RC-Line: Distributed RC Model R S (r w,c w,l) V out V in EE115C Winter

32 Design Rules of Thumb rc delays should only be considered when t prc >> t pgate of the driving gate: rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line when not met, the change in the signal is slower than the propagation delay of the wire M.J. Irwin, PSU, 2000 EE115C Winter

33 Outline Interconnect Capacitance Interconnect Resistance Modeling the Wire Perspective: Interconnect Issues EE115C Winter

34 Big Picture: Chip Packaging L Bonding Wire L Chip Lead Frame Pin Mounting Cavity Bond wires (~25mm) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100mm in 0.25mm technology), with large pitch (100mm) Many chips areas are pad limited EE115C Winter

35 Pad Frame Layout Die Photo EE115C Winter

36 Bonding Pad Design Bonding Pad GND 100 mm Out V DD In GND Out EE115C Winter

37 ESD Protection When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate need guard rings to pick it up. EE115C Winter

38 ESD Protection V DD PAD R D1 X D2 C Diode EE115C Winter

39 Diagonal Wiring destination y source x Manhattan 20+% Interconnect length reduction Clock speed - Signal integrity - Power integrity 15% Smaller chips plus 30% via reduction Courtesy Cadence X-initiative EE115C Winter