Effect of package parasitics and crosstalk on signal delay

Transcription

1 Effect of package parasitics and crosstalk on signal delay Francesc Moll and Miquel Roca Electronic Eng. Dpt. Univ. Polit. Catalunya UPC Physics Department Univ. Illes Balears UIB

2 Outline Introduction Objectives Simulation experiment Results Conclusions

3 Introduction Device size reduction Switching speed increasing Interconnection length increase Mix devices with different driving capabilities in same IC Increases probability of simultaneous activity Increases number of pins per chip

4 Technological trends Roadmap from SEMATECH (2000) Year Technology (nm) Gate oxide (nm) < 1.5 < 1.5 < 1.5 Metal levels 6/7 7 7/8 8/9 9 9/10 10 Transistors/cm 2 (SRAM) 35M 70M 95M 234M 577M 1423M 3514M Chip Area (mm 2 ) (DRAM) Memory (Bytes/chip) 1G 2G 4G 8G 20G 45G 104G Supply voltage (V) Power consumption (W) ft/fmax (GHz) 20/25 25/32 30/35 40/50 60/50 120/ /140 fclk (MHz) I/O serial (MHz) I/O paralel (MHz) Number of pins ASIC Number of pins MPU Cost/pin (10-2 x $)

5 Introduction Technological trends implications More important parasitic interaction

6 Noise sources Interconnect noise Introduction Coupling between lines Signal reflections and ringing Power supply distribution Simultaneous switching noise Noise at package level Related to simultaneous switching noise

7 Objectives Investigate different contributions on delay variation simultaneous transitions on neighboring lines (crosstalk) package parasitics (mainly switching noise)

8 Advanced vs Retarded Crosstalk delay

9 Simulation experiment Circuit considered

10 Package : DIL24 model P1 P2 P3 P4 P12 P24 P23 P22 P21 P13 Resistance 25-95mΩ Capacitance pF Inductance 9-19nH Ind. Coupling K

11 Input and Output PADS Schema & Transistors aspect ratio P P 22.5 N 8.5 N 15 P 22.5 N 12.5 P 62 N 40 P 192 N 120

12 Coupling structure I Six coupled chip lines length 1 mm minimum dimension Capacitance matrix from F.E.M. (Raphael (TMA)) SUBSTRATE

13 Coupling structure II two identical structures of six lines 2 chains of 10 inv (P 37.5, N 12.5) each set 10 Inv Quiet (reference delay) 10 inv P 37.5 N inv Active (noisy delay) 10 inv

14 Results Hspice Simulations Technology 0.7 micron ATMEL Rise and Fall times 500ps Delay in reference set vs Delay in noisy set Dependence on Package

15 Cases Analyzed

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22 Delay due to Package (without crosstalk)

23 Delay due to crosstalk (without package)

24 Difference delay due to crosstalk (with and without package)

25 Conclusions Crosstalk more important than Package in delay terms Package introduces noise in signals Future work Other packages Other circuits (core parts)