Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm
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1 EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1
2 Outline Scaling issues Technology scaling trends Features of modern technologies Lithography Process technologies 3 IC Design: Major Roadblocks 1. Managing complexity How to design a billion transistor chip? And what to use all these transistors for? 2. Cost of integrated circuits is increasing It takes >$M to design a chip Mask costs are more than $3M in 45nm technology 3. The end of frequency scaling - Power as a limiting factor Dealing with leakages 4. Robustness issues Variations, SRAM, soft errors, coupling 5. The interconnect problem 4 2
3 Moore s Law: Transistor Counts Transistor Counts in Intel's Microprocessors 00 Itanium II Trans sistors [in millions] DX 8088 Pentium 4 Pentium II Itanium Pentium Pro Pentium Pentium III 486DX Pentium MMX 486DX4 Doubles every 2 years Core2 5 Frequency Frequency Trends in Intel's Microprocessors requency [MHz] Fr DX 386DX Pentium II Pentium Pro Pentium 486DX4 Pentium III Pentium MMX Pentium 4 Core2 Itanium II Itanium 8088 Has been doubling every 2 years, but is now slowing down
4 Power Dissipation Power Trends in Intel's Microprocessors 00 Power [W] Has been > doubling every 2 years DX Pentium Pro Pentium Pentium III Itanium II Itanium Pentium II Pentium 4 Core DX Has to stay ~constant Some Recent Devices In production: 45nm high-k strained Si In research: nm device L = nm g K. Mistry, IEDM 07 Corresponds to sub-22nm node (~ years) 8 4
5 Some Recent Devices Intel s 30nm transistor, circa 2002 Ion = 570 m/ m Ioff = 60nA/ m [B. Doyle, Intel] 9 More Recent Devices Intel s 20nm transistor, circa [B. Doyle, Intel] 5
6 More Recent Devices Thin-Body SOI MOSFET SOI: Silicon-on-Insulator Cheng, IEDM Sub-5nm FinFET Gate Silicon Fin Source BOX Gate Drain Si fin - Body! X. Huang, et al, IEDM Lee, VLSI Technology,
7 Scaling Issues CMOS Scaling Rules Voltage, V / tox/ GATE WIRING W/ n+ source n+ drain L/ p substrate, doping *NA xd/ 11Å SCALING: Voltage: V/ Oxide: t ox / Wire width: W/ Gate width: L/ Diffusion: x d / Substrate: *N A R. H. Dennard et al., IEEE J. Solid State Circuits, (1974). RESULTS: Higher Density: ~ 2 Higher Speed: ~ Power/ckt: ~1/ 2 Power Density: ~Constant 14 7
8 Transistor Scaling Shrink by 30% 28nm F. Arnaud, IEDM 08 Contacted poly pitch 32nm transistor Shrink by 30% 15 Ideal vs. Real Scaling I DSAT [µa/µm] Ideal I DSAT 0 V DD [xv] 1 Ideal T inv Ideal V DD T inv [ps] V Th [V] Ideal V Th Lg [nm] Leakage slows down V Th, V DD scaling 16 8
9 Technology Flavors LP keeps drain leakage constant 17 Lg, R, C scaling 000 Nominal feature size 1 250nm 180nm 0.7X every 2 years 00 m Gate Length 130nm 90nm 65nm nm nm 50nm 45nm 32nm 22nm 0 35nm ~30nm With scaling L, need to scale up doping, to scale junction depth (control leakage) S/D resistance goes up External resistance limits current I V / R R D DS channel ext 18 9
10 Parasitic Capacitance Scaling S. Thompson, Materials Today, Reality: Overlap + fringe can be 50% of C channel in 32nm 19 45nm/32nm Technology Features
11 EE 141 Technology vs. 45nm FEOL 0.25 m features Lg ~ 240nm 248nm lithography No OPC, liberal design rules SiO 2 oxide, 3.5nm 6 dopant atoms LOCOS Nobody knew what is strain Velocity saturated No SD leakage No gate leakage One transistor flavor BEOL Al interconnect SiO 2 ILD 4-5 M layers No CMP, no density rules FEOL 45nm technology Lg = 35-40nm 193nm immersion lithography OPC, restricted design rules SiO2 oxide, 1.1nm (or Hf-based dielectric) < 3 dopant atoms STI Strained silicon in channel Velocity saturated I DS,off ~ 0nA/µm I g ~ na/µm 2 Many transistor flavors BEOL Cu interconnect Lo-k ILD 8- M layers CMP, density rules 21 Step-and-Scan Lithography 22 11
12 Lithography Scaling 000 Nominal feature size scaling m nm 248nm 193nm 250nm 180nm 130nm 90nm 65nm 45nm 32nm 22nm EUV Technology of the future (forever)? EUV 13nm 00 nm Sub-Wavelength Lithography Light projected through a gap 193nm light Mask Light intensity Light intensity 24 12
13 Sub-Wavelength Lithography CD k NA 1 Decrease Presently: 193 nm (ArF excimer laser) (Very) Distant Future: EUV Increase NA = nsinα Maximum n is 1 in air 193nm CDmin k nm Presently: ~ NA Immersion Result: Shrinking k1 45nm technology beyond resolution limit Presently: Theoretical Limit: Litho: How to Enhance Resolution? Immersion Off-axis illumination Optical proximity correction Phase-shifting masks Double patterning 26 13
14 Litho: Immersion Project through a drop of liquid n water = nm CD min k nm NA IBM 27 Litho: Illumination Regular Illumination Many off-axis designs (OAI) Annular Quadrupole / Quasar or Dipole + Amplifies certain pitches/rotations at expense of others A.Kahng, ICCAD
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