Crosstalk Limitations in Phantom Signal Transmission

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1 5 th IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS May 13-16, 2001, Venice (Cavallino), Italy Crosstalk Limitations in Phantom Signal Transmission Xavier Aragonès Electronic Engineering Dept. Univ. Politècnica de Catalunya Barcelona, Spain Thaddeus Gabara Bell Labs, Lucent Technologies (now with ) Murray Hill, NJ, USA

2 Introduction Rent s rule forecasts an increase of the number of I/O in an IC as a consequence of Moore s law. SIA roadmap: year 2001! year 2011 I/O (ASICs) 1100! 2700 I/O (MPU) 1024! 1408 Balanced digital transmission to reduce noise sensitivity, but uses double number of I/O (!).! We present a technique to transmit n-1 balanced signals with n interconnects, together with a study of its crosstalk limitations.

3 Balanced Transmission

4 Phantom Signaling

5 Ideal Driver for VLSI Systems Proposed driver for the transmission of one balanced signal: Robust and easy detection of received signal Easy control of the common-mode through the middle tap of the loads

6 3 Balanced Signals with 4 Wires

7 n-1 Balanced Signals with n Wires

8 n-1 Balanced Signals + 1 Single-ended with n Wires

9 SPICE simulation 0.16 µm CMOS technology, 3 V supply I=8 ma, V=±200 mv Pad capacitance / package parasitics (TQFP100) included in netlist current / voltage swing controlled with a reference circuit:

10 SPICE simulation A single random signal is transmitted over pair A, detected and fed back to pair B, detected and fed back to pair C (common-mode) 3.4 Gbps without errors (ideal interconnects)

11 SPICE simulation HSPICE embedded transmission line model for the interconnect Interconnect: ribbon cable with 50 mil pitch, 88 cm (35 inch) long Situation Max. Trans. Speed 2.5 Gbps 2.63 Gbps 2.86 Gbps 1.82 Gbps 1.96 Gbps

12 SPICE simulation Other wire assignments Situation Max. Trans. Speed 2.5 Gbps 1.85 Gbps 1.82 Gbps Speed degradation with increasing interconnect lenghts Interconnect length Max. Trans. Speed 127 mm (5 inch) 3.03 Gbps 508 mm (20 inch) 2.7 Gpbs 880 mm (35 inch) 2.5 Gbps 1270 mm (50 inch) 2.38 Gbps

13 Measurements Objectives: " Demonstrate that crosstalk does not prevent phantom signal transmission " Obtain experience previous to a VLSI implementation 2 PCBs with conventional resistors, SMA connectors, ribbon cable for the interconnects Adverse set-up: input signals from voltage (!) generators, with 50 Ω output impedance (!) and common grounds (!)

14 Measurements Even so, promising eye diagrams were obtained: signal A (or B) phantom signal (C)

15 Measurements Eye opening at the half-bit time measured: Situation eye opening of signal A / / eye opening of phantom signal (C) 420 mv / 170 mv 450 mv / 190 mv 540 mv / 160 mv 350 mv / 130 mv " Coherent with simulation results 510 mv / 130 mv

16 Measurements Other wire assignments Situation no GND plane 1 GND plane 2 GND planes 420 mv / 170 mv 450 mv / 190mV 540 mv / 160 mv 410 mv / 150 mv 480 mv / 130 mv 530 mv / 160 mv 240 mv / 80 mv 370 mv / 150 mv 500 mv / 150 mv Speed degradation with increasing interconnect lenghts eye opening of signal A / eye opening of phantom signal (C) 28 cm (11 inch) 560 mv / 208 mv 88 cm (35 inch) 450 mv / 190 mv

17 Measurements The phantom signal may be transmitted in the opposite direction (receiver to transmitter) signal A (or B) phantom signal (C) The phantom signal may be used for acknowledgement, or as a feedback to optimize speed / power consumption of the transmitter

18 Summary A system to transmit n-1 balanced signals (+1 single-ended) with n interconnects has been presented. A VLSI driver for this transmission system has been simulated, including package and interconnects parasitics, and coupling effects. Transmission rates in the range of 2 Gbps are predicted. A study has been presented to optimize the interconnect configuration, showing the importance of the grounding configuration to achieve maximum speed. Simple measurements show that crosstalk effects do not prevent phantom signal transmission. Good matching at the interfaces and low-parasitic package have shown to be capital for a successful transmission. A VLSI implementation of the system is on the way.

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